Texas Instruments TMS320C6745 DSP - PSC0 Module Error Clear Register 0 (Modules 0-15) (MERRCR0); PSC1 Module Error Clear Register 0 (Modules 0-31) (MERRCR0); PSC0 Module Error Clear Register 0 (MERRCR0); PSC1 Module Error Clear Register 0 (MERRCR0)

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SPRUH91D–March 2013–Revised September 2016
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Power and Sleep Controller (PSC)
8.6.5 PSC0 Module Error Clear Register 0 (modules 0-15) (MERRCR0)
The PSC0 module error clear register 0 (MERRCR0) is shown in Figure 8-5 and described in Table 8-11.
Figure 8-5. PSC0 Module Error Clear Register 0 (MERRCR0)
31 16
Reserved
R-0
15 14 0
M[15] Reserved
W-0 R-0
LEGEND: R = Read only; W = Write only; -n = value after reset
Table 8-11. PSC0 Module Error Clear Register 0 (MERRCR0) Field Descriptions
Bit Field Value Description
31-16 Reserved 0 Reserved
15 M[15] Clears the interrupt status bit (M[15]) set in the PSC0 module error pending register 0 (MERRPR0) and
the interrupt status bits set in the module status 15 register (MDSTAT15).
0 A write of 0 has no effect.
1 A write of 1 clears the M[15] bit in MERRPR0 and the EMUIHB and EMURST bits in MDSTAT15.
14-0 Reserved 0 Reserved
8.6.6 PSC1 Module Error Clear Register 0 (modules 0-31) (MERRCR0)
The PSC1 module error clear register 0 (MERRCR0) is shown in Figure 8-6.
Figure 8-6. PSC1 Module Error Clear Register 0 (MERRCR0)
31 0
Reserved
R-0
LEGEND: R = Read only; -n = value after reset