Texas Instruments TMS320C6745 DSP - Block Diagram Showing the Effects of the Digital Loopback Mode (DLB) Bit

ICDRR ICRSR
0
1
ICSAR
ICOAR
0
1
ICDXR
ICXSR
0
1
0
0
DLB
SCL_IN
SCL_OUT
Address/data
To internal I2C logic
From internal I2C logic
To internal I2C logic
To CPU or EDMA
From CPU or EDMA
From CPU or EDMA
From CPU or EDMA
SCLn
SDAn
I2C peripheral
DLB
DLB
www.ti.com Registers
919
SPRUH91D–March 2013–Revised September 2016
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Inter-Integrated Circuit (I2C) Module
Figure 22-23. Block Diagram Showing the Effects of the Digital Loopback Mode (DLB) Bit