www.ti.com
Registers
653
SPRUH91D–March 2013–Revised September 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
EMAC/MDIO Module
17.3.3.9 Transmit Interrupt Mask Set Register (TXINTMASKSET)
The transmit interrupt mask set register (TXINTMASKSET) is shown in Figure 17-47 and described in
Table 17-46.
Figure 17-47. Transmit Interrupt Mask Set Register (TXINTMASKSET)
31 16
Reserved
R-0
15 8
Reserved
R-0
7 6 5 4 3 2 1 0
TX7MASK TX6MASK TX5MASK TX4MASK TX3MASK TX2MASK TX1MASK TX0MASK
R/W1S-0 R/W1S-0 R/W1S-0 R/W1S-0 R/W1S-0 R/W1S-0 R/W1S-0 R/W1S-0
LEGEND: R/W = Read/Write; R = Read only; W1S = Write 1 to set (writing a 0 has no effect); -n = value after reset
Table 17-46. Transmit Interrupt Mask Set Register (TXINTMASKSET) Field Descriptions
Bit Field Value Description
31-8 Reserved 0 Reserved
7 TX7MASK 0-1 Transmit channel 7 interrupt mask set bit. Write 1 to enable interrupt, a write of 0 has no effect.
6 TX6MASK 0-1 Transmit channel 6 interrupt mask set bit. Write 1 to enable interrupt, a write of 0 has no effect.
5 TX5MASK 0-1 Transmit channel 5 interrupt mask set bit. Write 1 to enable interrupt, a write of 0 has no effect.
4 TX4MASK 0-1 Transmit channel 4 interrupt mask set bit. Write 1 to enable interrupt, a write of 0 has no effect.
3 TX3MASK 0-1 Transmit channel 3 interrupt mask set bit. Write 1 to enable interrupt, a write of 0 has no effect.
2 TX2MASK 0-1 Transmit channel 2 interrupt mask set bit. Write 1 to enable interrupt, a write of 0 has no effect.
1 TX1MASK 0-1 Transmit channel 1 interrupt mask set bit. Write 1 to enable interrupt, a write of 0 has no effect.
0 TX0MASK 0-1 Transmit channel 0 interrupt mask set bit. Write 1 to enable interrupt, a write of 0 has no effect.
To Next Page
Loading...
