Texas Instruments TMS320C6745 DSP - Purpose of the Peripheral

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16
SPRUH91D–March 2013–Revised September 2016
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Copyright © 2013–2016, Texas Instruments Incorporated
Contents
27.2.19 Initialization ................................................................................................... 1193
27.2.20 Timing Diagrams............................................................................................. 1194
27.3 Registers ................................................................................................................. 1200
27.3.1 SPI Global Control Register 0 (SPIGCR0)................................................................. 1200
27.3.2 SPI Global Control Register 1 (SPIGCR1)................................................................. 1201
27.3.3 SPI Interrupt Register (SPIINT0)............................................................................ 1203
27.3.4 SPI Interrupt Level Register (SPILVL)...................................................................... 1205
27.3.5 SPI Flag Register (SPIFLG) ................................................................................. 1206
27.3.6 SPI Pin Control Register 0 (SPIPC0) ...................................................................... 1208
27.3.7 SPI Pin Control Register 1 (SPIPC1)....................................................................... 1209
27.3.8 SPI Pin Control Register 2 (SPIPC2)....................................................................... 1210
27.3.9 SPI Pin Control Register 3 (SPIPC3)....................................................................... 1211
27.3.10 SPI Pin Control Register 4 (SPIPC4) ..................................................................... 1212
27.3.11 SPI Pin Control Register 5 (SPIPC5) ..................................................................... 1213
27.3.12 SPI Transmit Data Register 0 (SPIDAT0) ................................................................ 1214
27.3.13 SPI Transmit Data Register 1 (SPIDAT1) ................................................................ 1215
27.3.14 SPI Receive Buffer Register (SPIBUF) ................................................................... 1216
27.3.15 SPI Emulation Register (SPIEMU) ........................................................................ 1218
27.3.16 SPI Delay Register (SPIDELAY) .......................................................................... 1219
27.3.17 SPI Default Chip Select Register (SPIDEF).............................................................. 1222
27.3.18 SPI Data Format Registers (SPIFMTn)................................................................... 1223
27.3.19 SPI Interrupt Vector Register 1 (INTVEC1) .............................................................. 1225
28 64-Bit Timer Plus ............................................................................................................ 1226
28.1 Introduction............................................................................................................... 1227
28.1.1 Purpose of the Peripheral.................................................................................... 1227
28.1.2 Features ........................................................................................................ 1227
28.1.3 Block Diagram ................................................................................................. 1228
28.1.4 Industry Standard Compatibility Statement ................................................................ 1228
28.1.5 Architecture – General-Purpose Timer Mode ............................................................. 1228
28.1.6 Architecture – Watchdog Timer Mode...................................................................... 1240
28.1.7 Reset Considerations......................................................................................... 1242
28.1.8 Interrupt Support .............................................................................................. 1242
28.1.9 DMA Event Support........................................................................................... 1242
28.1.10 TM64P_OUT Event Support ............................................................................... 1243
28.1.11 Interrupt/DMA Event Generation Control and Status ................................................... 1244
28.1.12 Power Management ......................................................................................... 1244
28.1.13 Emulation Considerations .................................................................................. 1244
28.2 Registers ................................................................................................................. 1245
28.2.1 Revision ID Register (REVID) ............................................................................... 1247
28.2.2 Emulation Management Register (EMUMGT)............................................................. 1247
28.2.3 GPIO Interrupt Control and Enable Register (GPINTGPEN)............................................ 1248
28.2.4 GPIO Data and Direction Register (GPDATGPDIR) ..................................................... 1249
28.2.5 Timer Counter Registers (TIM12 and TIM34) ............................................................. 1250
28.2.6 Timer Period Registers (PRD12 and PRD34)............................................................. 1251
28.2.7 Timer Control Register (TCR) ............................................................................... 1252
28.2.8 Timer Global Control Register (TGCR)..................................................................... 1254
28.2.9 Watchdog Timer Control Register (WDTCR).............................................................. 1255
28.2.10 Timer Reload Register 12 (REL12) ....................................................................... 1256
28.2.11 Timer Reload Register 34 (REL34) ....................................................................... 1256
28.2.12 Timer Capture Register 12 (CAP12) ...................................................................... 1257
28.2.13 Timer Capture Register 34 (CAP34) ...................................................................... 1257
28.2.14 Timer Interrupt Control and Status Register (INTCTLSTAT) .......................................... 1258
29 Universal Asynchronous Receiver/Transmitter (UART) ....................................................... 1260