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SPRUH91D–March 2013–Revised September 2016
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External Memory Interface B (EMIFB)
Table 19-12. SDRAM/mobile SDRAM LOAD MODE REGISTER Command
A[9:7] A[6:4] A[3] A[2:0]
0 (Write bursts are
of the programmed
burst length in
EMB_A[2:0])
These bits control the CAS latency of the
SDRAM and are set according to CL field
in the SDRAM configuration register
(SDCFG) as follows:
• If CL = 2h, EMB_A[6:4] = 2h
(CAS latency = 2)
• If CL = 3h, EMB_A[6:4] = 3h
(CAS latency = 3)
0 (Sequential Burst
Type. Interleaved
Burst Type not
supported)
These bits control the burst length of the
SDRAM and are set according to the NM
field in the SDRAM configuration register
(SDCFG) as follows:
• If NM = 0, EMB_A[2:0] = 2h
(Burst Length = 4)
• If NM = 1, EMB_A[2:0] = 3h
(Burst Length = 8)
19.2.6.5 SDRAM Configuration Procedure
After initial power-on, follow the procedure listed below before performing any EMIFB memory requests.
Note that the SDRAM power-up constraint specifies that 200 μs must exist between receiving stable Vdd
and CLK and the issuing of a PRE command. Initialization software and system design must ensure that
this constraint is met before executing the initialization procedure.
1. Place the SDRAM into Self-Refresh Mode by setting the LP_MODE bit and SR_PD bit of the SDRAM
refresh control register (SDRFC) to 1 and 0, respectively. Place the SDRAM into Self-Refresh mode
when changing the frequency of EMB_CLK to avoid incurring the 200 μs power-up constraint again.
2. Program the PLL controller and configure the EMIFB clock mux selection (in the System Configuration
Module) to attain the desired EMB_CLK clock frequency. Refer to the device data manual for details
on programming the PLL controller. The frequency of the memory clock must meet the timing
requirements in the SDRAM manufacturer's documentation and the timing limitations shown in the
electrical specifications of the device data manual.
3. Enable SDR mode of the EMIFB by writing 1 to the SDREN bit (write 1 to both SDREN and
MSDRAM_ENABLE to enable mobile SDR) in the SDRAM configuration register (SDCFG). Also
ensure that pin multiplexing is properly configured.
4. Program SDTIM1 and SDTIM2 to satisfy the timing requirements for the attached SDRAM device.
Take the timing parameters from the SDRAM datasheet.
5. Program the REFRESH_RATE field of SDRFC to match that of the attached device's refresh interval.
See Section 19.2.6.6.1 for details on determining the appropriate value.
6. Program SDCFG to match the characteristics of the attached SDRAM device. This will cause the auto-
initialization sequence in Section 19.2.6.4 to be re-run. This second initialization generally takes much
less time due to the increased frequency of EMB_CLK.
After following the above procedure, the EMIFB is ready to perform accesses to the attached SDRAM
device. If a frequency change is desired after this configuration has been executed, first put the SDRAM
into Self-Refresh mode using a byte-write to the upper byte of SDCFG to avoid restarting the SDRAM
auto-initialization sequence. Then release the SDRAM from self-refresh mode and repeat steps 4 through
6 of the above procedure.
19.2.6.6 EMIFB Refresh Controller
An SDRAM device requires that each of its rows be refreshed at a minimum required rate. The EMIFB can
meet this constraint by performing auto refresh cycles at or above this required rate. An auto refresh cycle
consists of issuing a PRE command to all banks of the SDRAM device followed by issuing a REFR
command. To inform the EMIFB of the required rate for performing auto refresh cycles, the
REFRESH_RATE field of the SDRAM refresh control register (SDRFC) must be programmed. The EMIF
will use this value along with two internal counters to automatically perform auto refresh cycles at the
required rate. The auto refresh cycles cannot be disabled, even if the EMIFB is not interfaced with an
SDRAM. The remainder of this section details the EMIFB's refresh scheme and provides an example for
determining the appropriate value to place in the REFRESH_RATE field of SDRFC.
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