Texas Instruments TMS320C6745 DSP - EMIFA Timing Requirements for HY27 UA081 G1 M Example; NAND Flash Timing Requirements for HY27 UA081 G1 M Example

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SPRUH91D–March 2013–Revised September 2016
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External Memory Interface A (EMIFA)
18.3.2.3.3 Example Using Hynix HY27UA081G1M
This section takes you through the configuration steps required to implement Hynix’s HY27UA081G1M
NAND Flash with the EMIFA. The following assumptions are made:
• NAND Flash is connected to chip select space 2 (EMA_CS[2])
• EMIFA clock speed is 100 MHz (t
cyc
= 10 nS)
Table 18-44 lists the data sheet specifications for the EMIFA and Table 18-45 lists the data sheet
specifications for the NAND Flash.
(1)
Depending on operating conditions. See your device-specific data manual for the value.
Table 18-44. EMIFA Timing Requirements for HY27UA081G1M Example
Parameter Description Min Max Units
t
SU
Data Setup time, data valid before EMA_OE high 3 to 7
(1)
nS
t
H
Data Hold time, data valid after EMA_OE high 0 nS
Table 18-45. NAND Flash Timing Requirements for HY27UA081G1M Example
Parameter Description Min Max Units
t
RP
Read Pulse width 60 nS
t
REA
Read Enable Access time 60 nS
t
CEA
Chip Enable low to output valid 75 nS
t
CHZ
Chip Enable high to output High-Z 20 nS
t
RC
Read Cycle time 80 nS
t
RHZ
Read Enable high to output High-Z 30 nS
t
CLR
Command Latch low to Read enable low 10 nS
t
WP
Write Pulse width 60 nS
t
CLS
CLE Setup time 0 nS
t
ALS
ALE Setup time 0 nS
t
CS
CS Setup time 0 nS
t
DS
Data Setup time 20 nS
t
CLH
CLE Hold time 10 nS
t
ALH
ALE Hold time 10 nS
t
CH
CS Hold time 10 nS
t
DH
Data Hold time 10 nS
t
WC
Write Cycle time 80 nS