SYSCFG Registers
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SPRUH91D–March 2013–Revised September 2016
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System Configuration (SYSCFG) Module
10.5.9 Master Priority Registers (MSTPRI0-MSTPRI2)
10.5.9.1 Master Priority 0 Register (MSTPRI0)
The master priority 0 register (MSTPRI0) is shown in Figure 10-15 and described in Table 10-19.
Figure 10-15. Master Priority 0 Register (MSTPRI0)
31 30 28 27 26 24 23 22 20 19 18 16
Rsvd Reserved Rsvd Reserved Rsvd Reserved Rsvd Reserved
R/W-0 R/W-4h R/W-0 R/W-4h R/W-0 R/W-4h R/W-0 R/W-4h
15 14 12 11 10 8 7 6 4 3 2 0
Rsvd DSP_CFG Rsvd DSP_MDMA Rsvd Reserved Rsvd Reserved
R/W-0 R/W-2h R-0 R/W-2h R-0 R/W-2h R-0 R/W-2h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 10-19. Master Priority 0 Register (MSTPRI0) Field Descriptions
Bit Field Value Description
31 Reserved 0 Reserved. Write the default value when modifying this register.
30-28 Reserved 4h Reserved. Write the default value when modifying this register.
27 Reserved 0 Reserved. Write the default value when modifying this register.
26-24 Reserved 4h Reserved. Write the default value when modifying this register.
23 Reserved 0 Reserved. Write the default value when modifying this register.
22-20 Reserved 4h Reserved. Write the default value when modifying this register.
19 Reserved 0 Reserved. Write the default value when modifying this register.
18-16 Reserved 4h Reserved. Write the default value when modifying this register.
15 Reserved 0 Reserved. Write the default value when modifying this register.
14-12 DSP_CFG 0-7h DSP CFG port priority. Bit = 0 = priority 0 (highest); bit = 7h = priority 7 (lowest).
11 Reserved 0 Reserved. Always read as 0.
10-8 DSP_MDMA 0-7h DSP DMA port priority. Bit = 0 = priority 0 (highest); bit = 7h = priority 7 (lowest).
7 Reserved 0 Reserved. Always read as 0.
6-4 Reserved 2h Reserved. Write the default value when modifying this register.
3 Reserved 0 Reserved. Always read as 0.
2-0 Reserved 2h Reserved. Write the default value when modifying this register.