Texas Instruments TMS320C6745 DSP - TMS320 C6745;C6747 DSP System Interconnect Matrix; Introduction

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SPRUH91D–March 2013–Revised September 2016
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System Interconnect
3.1 Introduction
The DSP, the EDMA3 transfer controllers, and the device peripherals are interconnected through a switch
fabric architecture (see Section 3.2). The switch fabric is composed of multiple switched central resources
(SCRs) and multiple bridges. The SCRs establish low-latency connectivity between master peripherals
and slave peripherals.
Additionally, the SCRs provide priority-based arbitration and facilitate concurrent data movement between
master and slave peripherals. Through SCR, the DSP can send data to the EMIF without affecting a data
transfer between a device peripheral and internal shared memory. Bridges are mainly used to perform
bus-width conversion as well as bus operating frequency conversion.
The DSP, the EDMA3 transfer controllers, and the various device peripherals can be classified into two
categories: master peripherals and slave peripherals.
Master peripherals are typically capable of initiating read and write transfers in the system and do not rely
on the EDMA3 or on a CPU to perform transfers to and from them. The system master peripherals include
the DSP, the EDMA3 transfer controllers, EMAC, HPI, LCDC, and USB. Not all master peripherals may
connect to all slave peripherals. The supported connections are designated by an X in Table 3-1.
(1)
EDMA3TC group: EDMA3TC0, EDMA3TC1
(2)
Peripheral group: SYSCFG, EMAC, eCAP0, eCAP1, eCAP2, eHRPWM0, eHRPWM1, eHRPWM2, GPIO, I2C0, I2C1, LCDC,
McASP0, McASP1, McASP2, MDIO, MMC/SD, PLLC, PRU RAM0, PRU RAM1, PRU Config, PSC0, PSC1, RTC, SPI0, SPI1,
TIMER64P0, TIMER64P1, EDMA3CC0, UART0, UART1, UART2, HPI, USB0 (USB2.0), USB1 (USB1.1). The LCDC and
McASP2 are not supported on the C6745 DSP.
(3)
This peripheral is not supported on the C6745 DSP.
(4)
The HPI does not have access to all registers in the SYSCFG module because it operates with the User Privilege Level.
Table 3-1. TMS320C6745/C6747 DSP System Interconnect Matrix
Masters Slaves
Master
Default
Priority
DSP
SDMA EMIFA EMIFB 128 kB RAM
EDMA3TC
Group
(1)
Peripheral
Group
(2)
EDMA3CC0 0 X
EDMA3TC0 0 X X X X X X
EDMA3TC1 0 X X X X X X
PRU0 0 X X X X X X
PRU1 0 X X X X X X
DSP CFG 2 X X
DSP MDMA 2 X X X
EMAC 4 X X X X
USB2.0 4 X X X X
USB1.1
(3)
4 X X X X
LCDC
(3)
5 X
HPI
(3)
6 X X X X
(4)