Texas Instruments TMS320C6745 DSP - Counter Phase Control Register (CTRPHS); Capture 1 Register (CAP1); Counter Phase Control Register (CTRPHS) Field Descriptions; Capture 1 Register (CAP1) Field Descriptions

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SPRUH91D–March 2013–Revised September 2016
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Enhanced Capture (eCAP) Module
13.4.2 Counter Phase Control Register (CTRPHS)
The counter phase control register (CTRPHS) is shown in Figure 13-18 and described in Table 13-15.
Figure 13-18. Counter Phase Control Register (CTRPHS)
31 0
CTRPHS
R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
Table 13-15. Counter Phase Control Register (CTRPHS) Field Descriptions
Bit Field Value Description
31-0 CTRPHS 0-FFFF FFFFh Counter phase value register that can be programmed for phase lag/lead. This register
shadows TSCTR and is loaded into TSCTR upon either a SYNCI event or S/W force via a
control bit. Used to achieve phase control synchronization with respect to other eCAP and
EPWM time-bases.
13.4.3 Capture 1 Register (CAP1)
The capture 1 register (CAP1) is shown in Figure 13-19 and described in Table 13-16.
Figure 13-19. Capture 1 Register (CAP1)
31 0
CAP1
R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
Table 13-16. Capture 1 Register (CAP1) Field Descriptions
Bit Field Value Description
31-0 CAP1 0-FFFF FFFFh This register can be loaded (written) by:
• Time-Stamp (i.e., counter value) during a capture event
• Software - may be useful for test purposes
• APRD active register when used in APWM mode