Registers
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SPRUH91D–March 2013–Revised September 2016
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Multimedia Card (MMC)/Secure Digital (SD) Card Controller
25.4.2 MMC Memory Clock Control Register (MMCCLK)
The MMC memory clock control register (MMCCLK) is used to:
• Select whether the MMCSD_CLK pin is enabled or disabled (CLKEN bit).
• Select how much the function clock is divided-down to produce the memory clock (CLKRT bits). When
the MMCSD_CLK pin is enabled, the MMC controller drives the memory clock on this pin to control the
timing of communications with attached memory cards. For more details about clock generation, see
Section 25.2.1.
The MMC memory clock control register (MMCCLK) is shown in Figure 25-18 and described in Table 25-
7.
Figure 25-18. MMC Memory Clock Control Register (MMCCLK)
31 16
Reserved
R-0
15 10 9 8 7 0
Reserved DIV4 CLKEN CLKRT
R-0 R/W-0 R/W-0 R/W−FFh
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 25-7. MMC Memory Clock Control Register (MMCCLK) Field Descriptions
Bit Field Value Description
31-10 Reserved 0 Reserved
9 DIV4 DIV4 option
0 MMC clock = function clock/2 × (CLKRT + 1)
1 MMC clock = function clock/4 × (CLKRT + 1)
8 CLKEN MMCSD_CLK pin enable
0 MMCSD_CLK pin is disabled and fixed low
1 The MMCSD_CLK pin is enabled; it shows the memory clock signal.
7-0 CLKRT 0−FFh Clock rate. Use this field to set the divide-down value for the memory clock. The function clock is
divided down as follows to produce the memory clock:
memory clock frequency = function clock frequency/(2 × (CLKRT + 1) )
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