Registers
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SPRUH91D–March 2013–Revised September 2016
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Serial Peripheral Interface (SPI)
27.3.5 SPI Flag Register (SPIFLG)
The SPI flag register (SPIFLG) is shown in Figure 27-22 and described in Table 27-13.
Figure 27-22. SPI Flag Register (SPIFLG)
31 16
Reserved
R-100h
15 10 9 8
Reserved TXINTFLG RXINTFLG
R-0 R-0 R/WC-0
7 6 5 4 3 2 1 0
Reserved OVRNINTFLG Reserved BITERRFLG DESYNCFLG PARERRFLG TIMEOUTFLG DLENERRFLG
R-0 R/W1C-0 R-0 R/W1C-0 R/W1C-0 R/W1C-0 R/W1C-0 R/W1C-0
LEGEND: R/W = Read/Write; R = Read only; W1C = Write 1 to clear bit; -n = value after reset
Table 27-13. SPI Flag Register (SPIFLG) Field Descriptions
Bit Field Value Description
31-10 Reserved 4000h Reads return default value and writes have no effect.
9 TXINTFLG Transmitter empty interrupt flag. Serves as an interrupt flag indicating that the transmit buffer
(TXBUF) is empty and a new data can be written to it. This flag is set when a data is copied to the
shift register either directly or from the TXBUF register. This bit is cleared by one of following ways:
• Writing a new data to either SPIDAT0 or SPIDAT1
• Writing a 0 to SPIGCR1.ENABLE
0 Transmit buffer is now full. No interrupt pending for transmitter empty.
1 Transmit buffer is empty. An interrupt is pending to fill the transmitter.
8 RXINTFLG Receiver full interrupt flag. This flag is set when a word is received and copied into the buffer
register (SPIBUF). This bit is cleared under the following ways:
• Reading the SPIBUF register. During emulation mode, however, a read to the emulation register
(SPIEMU) does not clear this flag bit.
• Reading INTVEC1 register when there is a receive buffer full interrupt
• Writing a 1 to this bit
• Writing a 0 to SPIGCR1.ENABLE
• System reset
0 No new received data pending. Receive buffer is empty.
1 A newly received data is ready to be read. Receive buffer is full.
Note: Clearing RXINTFLG bit by writing a 1 before reading the SPIBUF sets the RXEMPTY bit of
the SPIBUF register too. This way, one can ignore a received data. However, if the internal RXBUF
is already full, the data from RXBUF will be copied to SPIBUF and the RXEMPTY bit will be cleared
again. The SPIBUF contents should be read first if this situation needs to be avoided.
7 Reserved 0 Reads return zero and writes have no effect.
6 OVRNINTFLG Receiver overrun flag. The bit is set when a receive operation completes before the previous
character has been read from the receive buffer. The bit indicates that the last received character
has been overwritten and therefore lost. This bit is cleared under the following conditions:
• Reading INTVEC1 register when there is a receive buffer overrun interrupt
• Writing a 1 to this bit
0 Overrun condition did not occur.
1 Overrun condition has occurred.
Note: Reading SPIBUF register does not clear the OVRNINTFLG bit. If an overrun interrupt is
detected, then the SPIBUF may need to be read twice to get to the overrun buffer. This is due to
the fact that the overrun will always occur to the internal RXBUF. Each read to the SPIBUF will
result in RXBUF contents (if it is full) getting copied to SPIBUF.
Note: A special condition under which OVRNINTFLG flag gets set. If both SPIBUF and RXBUF are
already full and while another buffer receive is underway, if any errors like TIMEOUT, BITERR and
DLENERR occur, then OVRNINTFLG will be set to indicate that the status flags are getting
overwritten by the new transfer. This overrun should be treated like a normal receiver overrun.
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