Texas Instruments TMS320C6745 DSP - 16.2.7 EDMA3 Channel Controller Regions; Shadow Region Registers

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SPRUH91D–March 2013–Revised September 2016
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Enhanced Direct Memory Access (EDMA3) Controller
16.2.7 EDMA3 Channel Controller Regions
The EDMA3 channel controller (EDMA3CC) divides its address space into multiple regions. Individual
channel resources can be exclusively assigned to a specific region, where each region is typically
assigned to a specific EDMA programmer. This allows partitioning of EDMA channel (DMA/QDMA)
resources in hetero- or multi-core devices, and devices where certain additional masters (for example,
coprocessors) can also program/initiate EDMA3 transfers. The application software running on these
cores/coprocessors can operate in these exclusive shadow region memory-maps, minimizing possibilities
of resource conflicts.
16.2.7.1 Region Overview
The EDMA3CC memory-mapped registers are divided in three main categories:
1. Global registers
2. Global region channel registers
3. Shadow region channel registers
The global registers are located at a single/fixed location in the EDMA3CC memory map. These registers
control EDMA3 resource mapping and provide debug visibility and error tracking information. See your
device-specific data manual for the EDMA3CC memory map.
The channel registers (including DMA, QDMA, and interrupt registers) are accessible via the global
channel region address range, or in the shadow n channel region address range(s). For example, the
event enable register (EER) is visible in the global region register space at offset 1020h, or region
addresses at offset 2020h for region 0 and at offset 2220h for region 1.
The underlying control register bits that are accessible via the shadow region address space (except for
IEVALn) are controlled by the DMA region access enable registers (DRAEm) and QDMA region access
enable registers (QRAEm). Table 16-6 lists the registers in the shadow region memory-map. (See
EDMA3CC memory-map figure for the complete global and shadow region memory-maps.) Figure 16-11
illustrates the conceptual view of the regions (where n is the number of shadow regions supported in the
EDMA3CC for a specific device).
Table 16-6. Shadow Region Registers
DRAEm QRAEm
ER QER
ECR QEER
ESR QEECR
CER QEESR
EER
EECR
EESR
SER
SECR
IER
IECR
IESR
IPR
ICR
Register not affected by DRAE
IEVAL