Texas Instruments TMS320C6745 DSP - Module ID Register (MIDR); Asynchronous Wait Cycle Configuration Register (AWCCR); Module ID Register (MIDR) Field Descriptions

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SPRUH91D–March 2013–Revised September 2016
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External Memory Interface A (EMIFA)
18.4.1 Module ID Register (MIDR)
This is a read-only register indicating the module ID of the EMIFA. The MIDR is shown in Figure 18-31
and described in Table 18-49.
Figure 18-31. Module ID Register (MIDR)
31 0
REV
R-4000 0205h
LEGEND: R = Read only; -n = value after reset
Table 18-49. Module ID Register (MIDR) Field Descriptions
Bit Field Value Description
31-0 REV 4000 0205h Module ID of EMIFA.
18.4.2 Asynchronous Wait Cycle Configuration Register (AWCC)
The asynchronous wait cycle configuration register (AWCC) is used to configure the parameters for
extended wait cycles. Both the polarity of the EMA_WAIT pin(s) and the maximum allowable number of
extended wait cycles can be configured. The AWCC is shown in Figure 18-32 and described in
Table 18-50. Not all devices support both EMA_WAIT[1] and EMA_WAIT[0], see the device-specific data
manual to determine support on each device.
NOTE: The EW bit in the asynchronous n configuration register (CE nCFG) must be set to allow for
the insertion of extended wait cycles.
Figure 18-32. Asynchronous Wait Cycle Configuration Register (AWCCR)
31 30 29 28 27 24 23 22 21 20 19 18 17 16
Reserved WP1 WP0 Reserved CS5_WAIT CS4_WAIT CS3_WAIT CS2_WAIT
R-0 R/W-1 R/W-1 R-0 R/W-0 R/W-0 R/W-0 R/W-0
15 8 7 0
Reserved MAX_EXT_WAIT
R-0 R/W-80h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset