Texas Instruments TMS320C6745 DSP - Counter-Compare Control Register (CMPCTL); Counter-Compare Control Register (CMPCTL) Field Descriptions

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SPRUH91D–March 2013–Revised September 2016
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Enhanced High-Resolution Pulse-Width Modulator (eHRPWM)
14.4.2.1 Counter-Compare Control Register (CMPCTL)
The counter-compare control register (CMPCTL) is shown in Figure 14-70 and described in Table 14-58.
Figure 14-70. Counter-Compare Control Register (CMPCTL)
15 10 9 8
Reserved SHDWBFULL SHDWAFULL
R-0 R-0 R-0
7 6 5 4 3 2 1 0
Reserved SHDWBMODE Reserved SHDWAMODE LOADBMODE LOADAMODE
R-0 R/W-0 R-0 R/W-0 R/W-0 R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 14-58. Counter-Compare Control Register (CMPCTL) Field Descriptions
Bits Name Value Description
15-10 Reserved 0 Reserved
9 SHDWBFULL Counter-compare B (CMPB) Shadow Register Full Status Flag. This bit self clears once a load-strobe
occurs.
0 CMPB shadow FIFO not full yet
1 Indicates the CMPB shadow FIFO is full; a CPU write will overwrite current shadow value.
8 SHDWAFULL Counter-compare A (CMPA) Shadow Register Full Status Flag. The flag bit is set when a 32-bit write to
CMPA:CMPAHR register or a 16-bit write to CMPA register is made. A 16-bit write to CMPAHR register
will not affect the flag. This bit self clears once a load-strobe occurs.
0 CMPA shadow FIFO not full yet
1 Indicates the CMPA shadow FIFO is full, a CPU write will overwrite the current shadow value.
7 Reserved 0 Reserved
6 SHDWBMODE Counter-compare B (CMPB) Register Operating Mode
0 Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register.
1 Immediate mode. Only the active compare B register is used. All writes and reads directly access the
active register for immediate compare action.
5 Reserved Reserved
4 SHDWAMODE Counter-compare A (CMPA) Register Operating Mode
0 Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register.
1 Immediate mode. Only the active compare register is used. All writes and reads directly access the
active register for immediate compare action
3-2 LOADBMODE 0-3h Active Counter-Compare B (CMPB) Load From Shadow Select Mode. This bit has no effect in
immediate mode (CMPCTL[SHDWBMODE] = 1).
0 Load on CTR = 0: Time-base counter equal to zero (TBCNT = 0000h)
1h Load on CTR = PRD: Time-base counter equal to period (TBCNT = TBPRD)
2h Load on either CTR = 0 or CTR = PRD
3h Freeze (no loads possible)
1-0 LOADAMODE 0-3h Active Counter-Compare A (CMPA) Load From Shadow Select Mode. This bit has no effect in
immediate mode (CMPCTL[SHDWAMODE] = 1).
0 Load on CTR = 0: Time-base counter equal to zero (TBCNT = 0000h)
1h Load on CTR = PRD: Time-base counter equal to period (TBCNT = TBPRD)
2h Load on either CTR = 0 or CTR = PRD
3h Freeze (no loads possible)