1180 0000h A4i
A12i
A3iA2iA1i
A9i A10i A11i
A7iA6iA5i
A13i ... ...
A8i
RSR RBR DRR
REVT
B6i
B9i B10i B11i B12i B13i ...
B1i B2i B3i B4i B5i
...
B8i
B7i
..B5..A5..B4..A4..B3..A3..B2..A2..B1..A1 01D0 0000h
1180 0080h
B6o
A6o
B2oB1o
B9o B10o
A9i A10i
B5oB4oB3o
B11o B12o B13o ...
A11i A12i A13i ...
A1o A2o A3o A4o A5o
B7o B8o
...
...
A8oA7o1180 1000h
1180 1080h
01D0 0004h
DXR
A1..B1..A2..B2..A3..B3..A4..B4..A5..B5
XSR
XEVT
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Transfer Examples
491
SPRUH91D–March 2013–Revised September 2016
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Enhanced Direct Memory Access (EDMA3) Controller
16.3.4.3 Continuous Operation
Configuring a DMA channel to receive a single frame of data is useful, and is applicable to some systems.
A majority of the time, however, data is going to be continuously transmitted and received throughout the
entire operation of the CPU. In this case, it is necessary to implement some form of linking such that the
DMA channels continuously reload the necessary parameter sets. In this example, the multichannel
buffered serial port (McBSP) is configured to transmit and receive data on a array. To simplify the
example, only two channels are active for both transmit and receive data streams. Each channel receives
packets of 128 elements. The packets are transferred from the serial port to L2 memory and from L2
memory to the serial port, as shown in Figure 16-25.
The McBSP generates REVT for every element received and generates XEVT for every element
transmitted. To service the data streams, the DMA channels associated with the McBSP must be set up
for 1D-to-1D transfers with A-synchronization.
Figure 16-26 shows the parameters for the parameter entries for the channel for these transfers. In order
to service the McBSP continuously throughout CPU operation, the channels must be linked to a duplicate
PaRAM set in the PaRAM. After all frames have been transferred, the DMA channels reload and continue.
Figure 16-27 shows the reload parameters for the channel.
16.3.4.3.1 Receive Channel
DMA channel 3 services the incoming data stream of the McBSP. The source address is set to that of the
data receiver register (DRR), and the destination address is set to the first element of the data block.
Since there are two data channels being serviced, A and B, they are to be located separately within the
L2 SRAM.
In order to facilitate continuous operation, a copy of the PaRAM set for the channel is placed in PaRAM
set 64. The LINK option is set and the link address is provided in the PaRAM set. Upon exhausting the
channel 3 parameter set, the parameters located at the link address are loaded into the channel 3
parameter set and operation continues. This function continues throughout device operation until halted by
the CPU.
16.3.4.3.2 Transmit Channel
DMA channel 2 services the outgoing data stream of the McBSP. In this case the destination address
needs no update, hence, the parameter set changes accordingly. Linking is also used to allow continuous
operation by the DMA channel, with duplicate PaRAM set entries at PaRAM set 65.
Figure 16-25. Servicing Continuous McBSP Data Example
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