Texas Instruments TMS320C6745 DSP - Interrupt Raw Status;Set Register (IRAWSTAT); Interrupt Raw Status;Set Register (IRAWSTAT) Field Descriptions

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SPRUH91D–March 2013–Revised September 2016
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Memory Protection Unit (MPU)
5.3.3 Interrupt Raw Status/Set Register (IRAWSTAT)
Reading the interrupt raw status/set register (IRAWSTAT) returns the status of all interrupts. Software can
write to IRAWSTAT to manually set an interrupt; however, an interrupt is generated only if the interrupt is
enabled in the interrupt enable set register (IENSET). Writes of 0 have no effect. The IRAWSTAT is
shown in Figure 5-5 and described in Table 5-10.
Figure 5-5. Interrupt Raw Status/Set Register (IRAWSTAT)
31 16
Reserved
R-0
15 2 1 0
Reserved ADDRERR PROTERR
R-0 R/W-0 R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 5-10. Interrupt Raw Status/Set Register (IRAWSTAT) Field Descriptions
Bit Field Value Description
31-2 Reserved 0 Reserved
1 ADDRERR Address violation error. Reading this bit reflects the status of the interrupt. Writing 1 sets the status;
writing 0 has no effect.
0 Interrupt is not set.
1 Interrupt is set.
0 PROTERR Protection violation error. Reading this bit reflects the status of the interrupt. Writing 1 sets the
status; writing 0 has no effect.
0 Interrupt is not set.
1 Interrupt is set.