Texas Instruments TMS320C6745 DSP - 18.2.9 EDMA Event Support; 18.2.10 Pin Multiplexing; 18.2.11 Memory Map; Interrupt Monitor and Control Bit Fields

www.ti.com Architecture
731
SPRUH91D–March 2013–Revised September 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
External Memory Interface A (EMIFA)
Table 18-25. Interrupt Monitor and Control Bit Fields
Register Name Bit Name Description
EMIFA interrupt raw register
(INTRAW)
WR This bit is set when an rising edge on the EMA_WAIT signal occurs. Writing
a 1 clears the WR bit as well as the WR_MASKED bit in INTMSK.
AT This bit is set when an asynchronous timeout occurs. Writing a 1 clears the
AT bit as well as the AT_MASKED bit in INTMSK.
LT This bit is set when an unsupported addressing mode is used. Writing a 1
clears LT bit as well as the LT_MASKED bit in INTMSK.
EMIFA interrupt mask register
(INTMSK)
WR_MASKED This bit is set only when a rising edge on the EMA_WAIT signal occurs and
the interrupt has been enabled by writing a 1 to the WR_MASK_SET bit in
INTMSKSET.
AT_MASKED This bit is set only when an asynchronous timeout occurs and the interrupt
has been enabled by writing a 1 to the AT_MASK_SET bit in INTMSKSET.
LT_MASKED This bit is set only when line trap interrupt occurs and the interrupt has been
enabled by writing a 1 to the LT_MASK_SET bit in INTMSKSET.
EMIFA interrupt mask set register
(INTMSKSET)
WR_MASK_SET Writing a 1 to this bit enables the wait rise interrupt.
AT_MASK_SET Writing a 1 to this bit enables the asynchronous timeout interrupt.
LT_MASK_SET Writing a 1 to this bit enables the line trap interrupt.
EMIFA interrupt mask clear register
(INTMSKCLR)
WR_MASK_CLR Writing a 1 to this bit disables the wait rise interrupt.
AT_MASK_CLR Writing a 1 to this bit disables the asynchronous timeout interrupt.
LT_MASK_CLR Writing a 1 to this bit disables the line trap interrupt.
18.2.8.2 Interrupt Multiplexing
For details on EMIFA interrupt multiplexing, see your device-specific data manual.
18.2.8.3 Interrupt Processing
For details on EMIFA interrupt processing, see the DSP Subsystem chapter .
For more details on the CPU's NMI interrupt, see the DSP Subsystem chapter and the TMS320C674x
CPU and Instruction Set Reference Guide (SPRUFE8).
18.2.9 EDMA Event Support
EMIFA memory controller is a DMA slave peripheral and therefore does not generate DMA events. Data
read and write requests may be made directly, by masters and the DMA.
18.2.10 Pin Multiplexing
For details on EMIFA pin multiplexing, see your device-specific data manual.
18.2.11 Memory Map
For information describing the device memory-map, see your device-specific data manual.