Texas Instruments TMS320C6745 DSP - 29.1.3 Functional Block Diagram; 29.2.2 Signal Descriptions; 29.2.9 DMA Event Support

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SPRUH91D–March 2013–Revised September 2016
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Contents
29.1 Introduction............................................................................................................... 1261
29.1.1 Purpose of the Peripheral.................................................................................... 1261
29.1.2 Features ........................................................................................................ 1261
29.1.3 Functional Block Diagram.................................................................................... 1261
29.1.4 Industry Standard(s) Compliance Statement .............................................................. 1261
29.2 Peripheral Architecture ................................................................................................. 1263
29.2.1 Clock Generation and Control ............................................................................... 1263
29.2.2 Signal Descriptions............................................................................................ 1265
29.2.3 Pin Multiplexing................................................................................................ 1265
29.2.4 Protocol Description .......................................................................................... 1265
29.2.5 Operation....................................................................................................... 1267
29.2.6 Reset Considerations......................................................................................... 1271
29.2.7 Initialization..................................................................................................... 1271
29.2.8 Interrupt Support .............................................................................................. 1271
29.2.9 DMA Event Support........................................................................................... 1273
29.2.10 Power Management ......................................................................................... 1273
29.2.11 Emulation Considerations .................................................................................. 1273
29.2.12 Exception Processing ....................................................................................... 1273
29.3 Registers ................................................................................................................. 1274
29.3.1 Receiver Buffer Register (RBR)............................................................................. 1275
29.3.2 Transmitter Holding Register (THR) ........................................................................ 1276
29.3.3 Interrupt Enable Register (IER) ............................................................................. 1277
29.3.4 Interrupt Identification Register (IIR)........................................................................ 1278
29.3.5 FIFO Control Register (FCR) ................................................................................ 1279
29.3.6 Line Control Register (LCR) ................................................................................. 1281
29.3.7 Modem Control Register (MCR)............................................................................. 1283
29.3.8 Line Status Register (LSR) .................................................................................. 1284
29.3.9 Modem Status Register (MSR).............................................................................. 1287
29.3.10 Scratch Pad Register (SCR) ............................................................................... 1288
29.3.11 Divisor Latches (DLL and DLH)............................................................................ 1288
29.3.12 Revision Identification Registers (REVID1 and REVID2) .............................................. 1290
29.3.13 Power and Emulation Management Register (PWREMU_MGMT) ................................... 1291
29.3.14 Mode Definition Register (MDR)........................................................................... 1292
30 Universal Serial Bus OHCI Host Controller......................................................................... 1293
30.1 Introduction............................................................................................................... 1294
30.1.1 Purpose of the Peripheral.................................................................................... 1294
30.2 Architecture .............................................................................................................. 1295
30.2.1 Clock and Reset .............................................................................................. 1295
30.2.2 Open Host Controller Interface Functionality .............................................................. 1296
30.2.3 Differences From OHCI Specification for USB ............................................................ 1296
30.2.4 Implementation of OHCI Specification for USB1.1 ....................................................... 1297
30.2.5 OHCI Interrupts................................................................................................ 1298
30.2.6 USB1.1 Host Controller Access to System Memory...................................................... 1298
30.2.7 Physical Addressing .......................................................................................... 1298
30.3 Registers ................................................................................................................. 1299
30.3.1 OHCI Revision Number Register (HCREVISION) ........................................................ 1300
30.3.2 HC Operating Mode Register (HCCONTROL) ............................................................ 1300
30.3.3 HC Command and Status Register (HCCOMMANDSTATUS).......................................... 1302
30.3.4 HC Interrupt and Status Register (HCINTERRUPTSTATUS)........................................... 1303
30.3.5 HC Interrupt Enable Register (HCINTERRUPTENABLE) ............................................... 1304
30.3.6 HC Interrupt Disable Register (HCINTERRUPTDISABLE).............................................. 1305
30.3.7 HC HCAA Address Register (HCHCCA)................................................................... 1306
30.3.8 HC Current Periodic Register (HCPERIODCURRENTED).............................................. 1306