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SYSCFG Registers
183
SPRUH91D–March 2013–Revised September 2016
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System Configuration (SYSCFG) Module
10.5.7.3 Interrupt Enable Register (IENSET)
The interrupt enable register (IENSET) allows setting/enabling the interrupt for address and/or protection
violation condition. It also shows the value of the register (whether or not interrupt is enabled). The
IENSET is shown in Figure 10-10 and described in Table 10-14.
Figure 10-10. Interrupt Enable Register (IENSET)
31 16
Reserved
R-0
15 2 1 0
Reserved ADDRERR_EN PROTERR_EN
R-0 R/W-0 R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 10-14. Interrupt Enable Register (IENSET) Field Descriptions
Bit Field Value Description
31-2 Reserved 0 Reserved. Always read 0.
1 ADDRERR_EN Addressing violation error.
0 Writing a 0 has not effect.
1 Writing a 1 enables this interrupt.
0 PROTERR_EN Protection violation error.
0 Writing a 0 has not effect.
1 Writing a 1 enables this interrupt.
10.5.7.4 Interrupt Enable Clear Register (IENCLR)
The interrupt enable clear register (IENCLR) allows clearing/disable the interrupt for address and/or
protection violation condition. It also shows the value of the interrupt enable register (IENSET). The
IENCLR is shown in Figure 10-11 and described in Table 10-15.
Figure 10-11. Interrupt Enable Clear Register (IENCLR)
31 16
Reserved
R-0
15 2 1 0
Reserved ADDRERR_CLR PROTERR_CLR
R-0 R/W-0 R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 10-15. Interrupt Enable Clear Register (IENCLR) Field Descriptions
Bit Field Value Description
31-2 Reserved 0 Reserved. Always read 0.
1 ADDRERR_CLR Addressing violation error.
0 Writing a 0 has not effect.
1 Writing a 1 clears/disables this interrupt.
0 PROTERR_CLR Protection violation error.
0 Writing a 0 has not effect.
1 Writing a 1 clears/disables this interrupt.
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