Registers
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SPRUH91D–March 2013–Revised September 2016
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General-Purpose Input/Output (GPIO)
20.3 Registers
Table 20-2 lists the memory-mapped registers for the general-purpose input/output (GPIO). The table
enumerates the registers required to support 144 GPIO pins, however not all devices will support 144
GPIO pins. For devices with less than 144 GPIO pins, assume that the extraneous fields and registers are
Reserved and serve no function. For devices with more than 144 GPIO pins, append registers and fields
as necessary using the address offset scheme in the table. See your device-specific data manual for the
number of GPIO pins supported and the base memory address for these registers.
Table 20-2. GPIO Registers
Offset Acronym Register Description Section
0h REVID Revision ID Register Section 20.3.1
8h BINTEN GPIO Interrupt Per-Bank Enable Register Section 20.3.2
GPIO Banks 0 and 1
10h DIR01 GPIO Banks 0 and 1 Direction Register Section 20.3.3
14h OUT_DATA01 GPIO Banks 0 and 1 Output Data Register Section 20.3.4
18h SET_DATA01 GPIO Banks 0 and 1 Set Data Register Section 20.3.5
1Ch CLR_DATA01 GPIO Banks 0 and 1 Clear Data Register Section 20.3.6
20h IN_DATA01 GPIO Banks 0 and 1 Input Data Register Section 20.3.7
24h SET_RIS_TRIG01 GPIO Banks 0 and 1 Set Rising Edge Interrupt Register Section 20.3.8
28h CLR_RIS_TRIG01 GPIO Banks 0 and 1 Clear Rising Edge Interrupt Register Section 20.3.9
2Ch SET_FAL_TRIG01 GPIO Banks 0 and 1 Set Falling Edge Interrupt Register Section 20.3.10
30h CLR_FAL_TRIG01 GPIO Banks 0 and 1 Clear Falling Edge Interrupt Register Section 20.3.11
34h INTSTAT01 GPIO Banks 0 and 1 Interrupt Status Register Section 20.3.12
GPIO Banks 2 and 3
38h DIR23 GPIO Banks 2 and 3 Direction Register Section 20.3.3
3Ch OUT_DATA23 GPIO Banks 2 and 3 Output Data Register Section 20.3.4
40h SET_DATA23 GPIO Banks 2 and 3 Set Data Register Section 20.3.5
44h CLR_DATA23 GPIO Banks 2 and 3 Clear Data Register Section 20.3.6
48h IN_DATA23 GPIO Banks 2 and 3 Input Data Register Section 20.3.7
4Ch SET_RIS_TRIG23 GPIO Banks 2 and 3 Set Rising Edge Interrupt Register Section 20.3.8
50h CLR_RIS_TRIG23 GPIO Banks 2 and 3 Clear Rising Edge Interrupt Register Section 20.3.9
54h SET_FAL_TRIG23 GPIO Banks 2 and 3 Set Falling Edge Interrupt Register Section 20.3.10
58h CLR_FAL_TRIG23 GPIO Banks 2 and 3 Clear Falling Edge Interrupt Register Section 20.3.11
5Ch INTSTAT23 GPIO Banks 2 and 3 Interrupt Status Register Section 20.3.12
GPIO Banks 4 and 5
60h DIR45 GPIO Banks 4 and 5 Direction Register Section 20.3.3
64h OUT_DATA45 GPIO Banks 4 and 5 Output Data Register Section 20.3.4
68h SET_DATA45 GPIO Banks 4 and 5 Set Data Register Section 20.3.5
6Ch CLR_DATA45 GPIO Banks 4 and 5 Clear Data Register Section 20.3.6
70h IN_DATA45 GPIO Banks 4 and 5 Input Data Register Section 20.3.7
74h SET_RIS_TRIG45 GPIO Banks 4 and 5 Set Rising Edge Interrupt Register Section 20.3.8
78h CLR_RIS_TRIG45 GPIO Banks 4 and 5 Clear Rising Edge Interrupt Register Section 20.3.9
7Ch SET_FAL_TRIG45 GPIO Banks 4 and 5 Set Falling Edge Interrupt Register Section 20.3.10
80h CLR_FAL_TRIG45 GPIO Banks 4 and 5 Clear Falling Edge Interrupt Register Section 20.3.11
84h INTSTAT45 GPIO Banks 4 and 5 Interrupt Status Register Section 20.3.12
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