Registers
www.ti.com
1124
SPRUH91D–March 2013–Revised September 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
Multimedia Card (MMC)/Secure Digital (SD) Card Controller
25.3.10.3 SDIO Interrupt Control Registers (SDIOIEN, SDIOIST)
The SDIO card controller issues an interrupt to the CPU when the read wait operation starts or when an
SDIO interrupt is detected on the SD_DATA1 line.
Interrupt flags of each case are checked with the SDIO interrupt status register (SDIOIST). To issue an
actual interrupt to the CPU, enabling each interrupt in the SDIO interrupt enable register (SDIOIEN) is
required.
When both interrupts are enabled, they are both reported to the CPU as an interrupt (whether one or both
occurred). The interrupt(s) that occurred are determined by reading SDIOIST.
25.4 Registers
Table 25-5 lists the memory-mapped registers for the multimedia card/secure digital (MMC/SD) card
controller. See your device-specific data manual for the memory address of these registers.
Table 25-5. Multimedia Card/Secure Digital (MMC/SD) Card Controller Registers
Offset Acronym Register Description Section
0h MMCCTL MMC Control Register Section 25.4.1
4h MMCCLK MMC Memory Clock Control Register Section 25.4.2
8h MMCST0 MMC Status Register 0 Section 25.4.3
Ch MMCST1 MMC Status Register 1 Section 25.4.4
10h MMCIM MMC Interrupt Mask Register Section 25.4.5
14h MMCTOR MMC Response Time-Out Register Section 25.4.6
18h MMCTOD MMC Data Read Time-Out Register Section 25.4.7
1Ch MMCBLEN MMC Block Length Register Section 25.4.8
20h MMCNBLK MMC Number of Blocks Register Section 25.4.9
24h MMCNBLC MMC Number of Blocks Counter Register Section 25.4.10
28h MMCDRR MMC Data Receive Register Section 25.4.11
2Ch MMCDXR MMC Data Transmit Register Section 25.4.12
30h MMCCMD MMC Command Register Section 25.4.13
34h MMCARGHL MMC Argument Register Section 25.4.14
38h MMCRSP01 MMC Response Register 0 and 1 Section 25.4.15
3Ch MMCRSP23 MMC Response Register 2 and 3 Section 25.4.15
40h MMCRSP45 MMC Response Register 4 and 5 Section 25.4.15
44h MMCRSP67 MMC Response Register 6 and 7 Section 25.4.15
48h MMCDRSP MMC Data Response Register Section 25.4.16
50h MMCCIDX MMC Command Index Register Section 25.4.17
64h SDIOCTL SDIO Control Register Section 25.4.18
68h SDIOST0 SDIO Status Register 0 Section 25.4.19
6Ch SDIOIEN SDIO Interrupt Enable Register Section 25.4.20
70h SDIOIST SDIO Interrupt Status Register Section 25.4.21
74h MMCFIFOCTL MMC FIFO Control Register Section 25.4.22
To Next Page
Loading...
