Texas Instruments TMS320C6745 DSP - Eqep Interrupt Flag Register (QFLG); Eqep Interrupt Flag Register (QFLG) Field Descriptions

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SPRUH91D–March 2013–Revised September 2016
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Enhanced Quadrature Encoder Pulse (eQEP) Module
15.3.17 eQEP Interrupt Flag Register (QFLG)
Figure 15-37. eQEP Interrupt Flag Register (QFLG)
15 12 11 10 9 8
Reserved UTO IEL SEL PCM
R-0 R-0 R-0 R-0 R-0
7 6 5 4 3 2 1 0
PCR PCO PCU WTO QDC PHE PCE INT
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
LEGEND: R = Read only; -n = value after reset
Table 15-19. eQEP Interrupt Flag Register (QFLG) Field Descriptions
Bits Name Value Description
15-12 Reserved 0 Always write as 0
11 UTO Unit time out interrupt flag
0 No interrupt generated
1 Set by eQEP unit timer period match
10 IEL Index event latch interrupt flag
0 No interrupt generated
1 This bit is set after latching the QPOSCNT to QPOSILAT
9 SEL Strobe event latch interrupt flag
0 No interrupt generated
1 This bit is set after latching the QPOSCNT to QPOSSLAT
8 PCM eQEP compare match event interrupt flag
0 No interrupt generated
1 This bit is set on position-compare match
7 PCR Position-compare ready interrupt flag
0 No interrupt generated
1 This bit is set after transferring the shadow register value to the active position compare register.
6 PCO Position counter overflow interrupt flag
0 No interrupt generated
1 This bit is set on position counter overflow.
5 PCU Position counter underflow interrupt flag
0 No interrupt generated
1 This bit is set on position counter underflow.
4 WTO Watchdog timeout interrupt flag
0 No interrupt generated
1 Set by watch dog timeout
3 QDC Quadrature direction change interrupt flag
0 No interrupt generated
1 This bit is set during change of direction
2 PHE Quadrature phase error interrupt flag
0 No interrupt generated
1 Set on simultaneous transition of QEPA and QEPB
1 PCE Position counter error interrupt flag
0 No interrupt generated
1 Position counter error