Texas Instruments TMS320C6745 DSP - PLL Post-Divider Control Register (POSTDIV); PLL Controller Command Register (PLLCMD); PLL Post-Divider Control Register (POSTDIV) Field Descriptions; PLL Controller Command Register (PLLCMD) Field Descriptions

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SPRUH91D–March 2013–Revised September 2016
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Phase-Locked Loop Controller (PLLC)
7.4.15 PLL Post-Divider Control Register (POSTDIV)
The PLL post-divider control register (POSTDIV) is shown in Figure 7-16 and described in Table 7-17.
Figure 7-16. PLL Post-Divider Control Register (POSTDIV)
31 16
Reserved
R-0
15 14 5 4 0
POSTDEN Reserved RATIO
R/W-1 R-0 R/W-1
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 7-17. PLL Post-Divider Control Register (POSTDIV) Field Descriptions
Bit Field Value Description
31-16 Reserved 0 Reserved
15 POSTDEN Post_Divider enable.
0 Disable
1 Enable
14-5 Reserved 0 Reserved
4-0 RATIO 0-1Fh Divider ratio. Divider Value = RATIO + 1. RATIO defaults to 1 (PLL post-divide by 2).
7.4.16 PLL Controller Command Register (PLLCMD)
The PLL controller command register (PLLCMD) is shown in Figure 7-17 and described in Table 7-18.
contains command bits for various operations. Writes of 1 initiate command; writes of 0 clear the bit, but
have no effect.
Figure 7-17. PLL Controller Command Register (PLLCMD)
31 16
Reserved
R-0
15 1 0
Reserved GOSET
R-0 R/W0C-0
LEGEND: R/W = Read/Write; R = Read only; W0C = Write 0 to clear bit; -n = value after reset
Table 7-18. PLL Controller Command Register (PLLCMD) Field Descriptions
Bit Field Value Description
31-1 Reserved 0 Reserved
0 GOSET GO bit for SYSCLKx phase alignment.
0 Clear bit (no effect)
1 Phase alignment