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Registers
535
SPRUH91D–March 2013–Revised September 2016
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Enhanced Direct Memory Access (EDMA3) Controller
16.4.2.5.8 Secondary Event Register (SER)
The secondary event register (SER) provides information on the state of a DMA channel or event (0
through 31). If the EDMA3CC receives a TR synchronization due to a manual-trigger, event-trigger, or
chained-trigger source (ESR.En = 1, ER.En = 1, or CER.En = 1), which results in the setting of a
corresponding event bit in SER (SER.En = 1), it implies that the corresponding DMA event is in the queue.
Once a bit corresponding to an event is set in SER, the EDMA3CC does not prioritize additional events on
the same DMA channel. Depending on the condition that leads to the setting of the SER bits, either the
EDMA3CC hardware or the software (using SECR) needs to clear the SER bits for the EDMA3CC to
evaluate subsequent events and perform subsequent transfers on the same channel. Based on whether
the associated TR is valid, or it is a null or dummy TR, the implications on the state of SER and the
required user action in order to submit another DMA transfer might be different.
The SER is shown in Figure 16-68 and described in Table 16-47.
Figure 16-68. Secondary Event Register (SER)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
E31 E30 E29 E28 E27 E26 E25 E24 E23 E22 E21 E20 E19 E18 E17 E16
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
E15 E14 E13 E12 E11 E10 E9 E8 E7 E6 E5 E4 E3 E2 E1 E0
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
LEGEND: R = Read only; -n = value after reset
Table 16-47. Secondary Event Register (SER) Field Descriptions
Bit Field Value Description
31-0 En Secondary event register. The secondary event register is used to provide information on the state of an
event.
0 Event is not currently stored in the event queue.
1 Event is currently stored in the event queue. Event arbiter will not prioritize additional events.
16.4.2.5.9 Secondary Event Clear Register (SECR)
The secondary event clear register (SECR) clears the status of the secondary event registers (SER). CPU
writes of 1 clear the corresponding set bits in SER. Writes of 0 have no effect.
The SECR is shown in Figure 16-69 and described in Table 16-48.
Figure 16-69. Secondary Event Clear Register (SECR)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
E31 E30 E29 E28 E27 E26 E25 E24 E23 E22 E21 E20 E19 E18 E17 E16
W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
E15 E14 E13 E12 E11 E10 E9 E8 E7 E6 E5 E4 E3 E2 E1 E0
W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0
LEGEND: W = Write only; -n = value after reset
Table 16-48. Secondary Event Clear Register (SECR) Field Descriptions
Bit Field Value Description
31-0 En Secondary event clear register
0 No effect.
1 Corresponding bit in the secondary event register (SER) is cleared (En = 0).
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