Registers
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SPRUH91D–March 2013–Revised September 2016
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Enhanced Direct Memory Access (EDMA3) Controller
16.4.2.4.3 Queue Watermark Threshold A Register (QWMTHRA)
The queue watermark threshold A register (QWMTHRA) is shown in Figure 16-59 and described in
Table 16-38.
Figure 16-59. Queue Watermark Threshold A Register (QWMTHRA)
31 16
Reserved
R-0
15 13 12 8 7 5 4 0
Reserved Q1 Reserved Q0
R-0 R/W-10h R-0 R/W-10h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 16-38. Queue Watermark Threshold A Register (QWMTHRA) Field Descriptions
Bit Field Value Description
31-13 Reserved 0 Reserved
12-8 Q1 0-1Fh Queue threshold for queue 1 value. The QTHRXCD1 bit in the EDMA3CC error register (CCERR)
and the THRXCD bit in the queue status register 1 (QSTAT1) are set when the number of events
in queue 1 at an instant in time (visible via the NUMVAL bit in QSTAT1) equals or exceeds the
value specified by Q1.
0-10h The default is 16 (maximum allowed).
11h Disables the threshold errors.
12h-1Fh Reserved
7-5 Reserved 0 Reserved
4-0 Q0 0-1Fh Queue threshold for queue 0 value. The QTHRXCD0 bit in the EDMA3CC error register (CCERR)
and the THRXCD bit in the queue status register 0 (QSTAT0) are set when the number of events
in queue 0 at an instant in time (visible via the NUMVAL bit in QSTAT0) equals or exceeds the
value specified by Q0.
0-10h The default is 16 (maximum allowed).
11h Disables the threshold errors.
12h-1Fh Reserved
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