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SPRUH91D–March 2013–Revised September 2016
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Inter-Integrated Circuit (I2C) Module
22.2.8 NACK Bit Generation
When the I2C peripheral is a receiver (master or slave), it can acknowledge or ignore bits sent by the
transmitter. To ignore any new bits, the I2C peripheral must send a no-acknowledge (NACK) bit during the
acknowledge cycle on the bus. Table 22-2 summarizes the various ways the I2C peripheral sends a
NACK bit.
Table 22-2. Ways to Generate a NACK Bit
NACK Bit Generation
I2C Peripheral
Condition Basic Optional
Slave-receiver mode
• Disable data transfers (STT = 0 in ICSTR).
• Allow an overrun condition (RSFULL = 1 in
ICSTR).
• Reset the peripheral (IRS = 0 in ICMDR)
.
Set the NACKMOD bit of ICMDR before the rising
edge of the last data bit you intend to receive.
Master-receiver mode
AND
Repeat mode
(RM = 1 in ICMDR)
• Generate a STOP condition (STOP = 1 in
ICMDR).
• Reset the peripheral (IRS = 0 in ICMDR).
Set the NACKMOD bit of ICMDR before the rising
edge of the last data bit you intend to receive.
Master-receiver mode
AND
Nonrepeat mode
(RM = 0 in ICMDR)
• If STP = 1 in ICMDR, allow the internal data
counter to count down to 0 and force a STOP
condition.
• If STP = 0, make STP = 1 to generate a
STOP condition.
• Reset the peripheral (IRS = 0 in ICMDR).
Set the NACKMOD bit of ICMDR before the rising
edge of the last data bit you intend to receive.
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