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Texas Instruments TMS320C6745 DSP - Destination FIFO Options Register N (Dfoptn); Destination FIFO Options Register N (Dfoptn) Field Descriptions

Texas Instruments TMS320C6745 DSP
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Registers
563
SPRUH91DMarch 2013Revised September 2016
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Copyright © 2013–2016, Texas Instruments Incorporated
Enhanced Direct Memory Access (EDMA3) Controller
16.4.3.6.13 Destination FIFO Options Register n (DFOPTn)
The destination FIFO options register n (DFOPTn) is shown in Figure 16-103 and described in
Table 16-83.
Figure 16-103. Destination FIFO Options Register n (DFOPTn)
31 23 22 21 20 19 18 17 16
Reserved TCCHEN Rsvd TCINTEN Reserved TCC
R-0 R/W-0 R-0 R/W-0 R-0 R/W-0
15 12 11 10 8 7 6 4 3 2 1 0
TCC Rsvd FWID Rsvd PRI Reserved DAM SAM
R/W-0 R-0 R/W-0 R-0 R/W-0 R-0 R/W-0 R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 16-83. Destination FIFO Options Register n (DFOPTn) Field Descriptions
Bit Field Value Description
31-23 Reserved 0 Reserved
22 TCCHEN Transfer complete chaining enable.
0 Transfer complete chaining is disabled.
1 Transfer complete chaining is enabled.
21 Reserved 0 Reserved
20 TCINTEN Transfer complete interrupt enable.
0 Transfer complete interrupt is disabled.
1 Transfer complete interrupt is enabled.
19-18 Reserved 0 Reserved
17-12 TCC 0-3Fh Transfer complete code. This 6-bit code is used to set the relevant bit in CER or IPR of the EDMA3CC.
11 Reserved 0 Reserved
10-8 FWID 0-7h FIFO width. Applies if either SAM or DAM is set to constant addressing mode.
0 FIFO width is 8 bits.
1h FIFO width is 16 bits.
2h FIFO width is 32 bits.
3h FIFO width is 64 bits.
4h FIFO width is 128 bits.
5h-7h Reserved
7 Reserved 0 Reserved
6-4 PRI 0-7h Transfer priority.
0 Priority 0 - Highest priority
1h-6h Priority 1 to priority 6
7h Priority 7 - Lowest priority
3-2 Reserved 0 Reserved
1 DAM Destination address mode within an array.
0 Increment (INCR) mode. Destination addressing within an array increments.
1 Constant addressing (CONST) mode. Destination addressing within an array wraps around upon
reaching FIFO width.
0 SAM Source address mode within an array.
0 Increment (INCR) mode. Source addressing within an array increments.
1 Constant addressing (CONST) mode. Source addressing within an array wraps around upon reaching
FIFO width.

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