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Registers
515
SPRUH91D–March 2013–Revised September 2016
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Enhanced Direct Memory Access (EDMA3) Controller
16.4.2.2 Error Registers
The EDMA3CC contains a set of registers that provide information on missed DMA and/or QDMA events,
and instances when event queue thresholds are exceeded. If any of the bits in these registers is set, it
results in the EDMA3CC generating an error interrupt.
16.4.2.2.1 Event Missed Registers (EMR)
For a particular DMA channel, if a second event is received prior to the first event getting cleared/serviced,
the bit corresponding to that channel is set/asserted in the event missed register (EMR). All trigger types
are treated individually, that is, manual triggered (ESR), chain triggered (CER), and event triggered (ER)
are all treated separately. The EMR bit for a channel is also set if an event on that channel encounters a
NULL entry (or a NULL TR is serviced). If any EMR bit is set (and all errors, including bits in other error
registers (QEMR, CCERR) were previously cleared), the EDMA3CC generates an error interrupt. See
Section 16.2.9.4 for details on EDMA3CC error interrupt generation.
The EMR is shown in Figure 16-48 and described in Table 16-27.
Figure 16-48. Event Missed Register (EMR)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
E31 E30 E29 E28 E27 E26 E25 E24 E23 E22 E21 E20 E19 E18 E17 E16
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
E15 E14 E13 E12 E11 E10 E9 E8 E7 E6 E5 E4 E3 E2 E1 E0
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
LEGEND: R = Read only; -n = value after reset
Table 16-27. Event Missed Register (EMR) Field Descriptions
Bit Field Value Description
31-0 En Channel 0-31 event missed. En is cleared by writing a 1 to the corresponding bit in the event missed clear
register (EMCR).
0 No missed event.
1 Missed event occurred.
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