Texas Instruments TMS320C6745 DSP - Event Missed Clear Register (EMCR); Event Missed Clear Register (EMCR) Field Descriptions

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SPRUH91D–March 2013–Revised September 2016
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Enhanced Direct Memory Access (EDMA3) Controller
16.4.2.2.2 Event Missed Clear Registers (EMCR)
Once a missed event is posted in the event missed register (EMR), the bit remains set and you need to
clear the set bit(s). This is done by way of CPU writes to the event missed clear register (EMCR). Writing
a 1 to any of the bits clears the corresponding missed event (bit) in EMR; writing a 0 has no effect.
The EMCR is shown in Figure 16-49 and described in Table 16-28.
Figure 16-49. Event Missed Clear Register (EMCR)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
E31 E30 E29 E28 E27 E26 E25 E24 E23 E22 E21 E20 E19 E18 E17 E16
W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
E15 E14 E13 E12 E11 E10 E9 E8 E7 E6 E5 E4 E3 E2 E1 E0
W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0
LEGEND: W = Write only; -n = value after reset
Table 16-28. Event Missed Clear Register (EMCR) Field Descriptions
Bit Field Value Description
31-0 En Event missed 0-31 clear. All error bits must be cleared before additional error interrupts will be asserted
by the EDMA3CC.
0 No effect.
1 Corresponding missed event bit in the event missed register (EMR) is cleared (En = 0).