Texas Instruments TMS320C6745 DSP - Time-Base Control Register (TBCTL) Field Descriptions

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SPRUH91D–March 2013–Revised September 2016
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Enhanced High-Resolution Pulse-Width Modulator (eHRPWM)
Table 14-52. Time-Base Control Register (TBCTL) Field Descriptions
Bit Field Value Description
15-14 FREE, SOFT 0-3h Emulation Mode Bits. These bits select the behavior of the ePWM time-base counter during
emulation events:
0 Stop after the next time-base counter increment or decrement
1h Stop when counter completes a whole cycle:
• Up-count mode: stop when the time-base counter = period (TBCNT = TBPRD)
• Down-count mode: stop when the time-base counter = 0000 (TBCNT = 0000h)
• Up-down-count mode: stop when the time-base counter = 0000 (TBCNT = 0000h)
2h-3h Free run
13 PHSDIR Phase Direction Bit. This bit is only used when the time-base counter is configured in the up-down-
count mode. The PHSDIR bit indicates the direction the time-base counter (TBCNT) will count after
a synchronization event occurs and a new phase value is loaded from the phase (TBPHS) register.
This is irrespective of the direction of the counter before the synchronization event..
In the up-count and down-count modes this bit is ignored.
0 Count down after the synchronization event.
1 Count up after the synchronization event.
12:10 CLKDIV 0-7h Time-base Clock Prescale Bits. These bits determine part of the time-base clock prescale value.
TBCLK = SYSCLKOUT/(HSPCLKDIV × CLKDIV)
0 /1 (default on reset)
1h /2
2h /4
3h /8
4h /16
5h /32
6h /64
7h /128
9-7 HSPCLKDIV 0-7h High-Speed Time-base Clock Prescale Bits. These bits determine part of the time-base clock
prescale value.
TBCLK = SYSCLKOUT/(HSPCLKDIV × CLKDIV)
This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager
(EV) peripheral.
0 /1
1h /2 (default on reset)
2h /4
3h /6
4h /8
5h /10
6h /12
7h /14
6 SWFSYNC Software Forced Synchronization Pulse
0 Writing a 0 has no effect and reads always return a 0.
1 Writing a 1 forces a one-time synchronization pulse to be generated.
This event is ORed with the EPWMxSYNCI input of the ePWM module.
SWFSYNC is valid (operates) only when EPWMxSYNCI is selected by SYNCOSEL = 00.
5-4 SYNCOSEL 0-3h Synchronization Output Select. These bits select the source of the EPWMxSYNCO signal.
0 EPWMxSYNC:
1h CTR = 0: Time-base counter equal to zero (TBCNT = 0000h)
2h CTR = CMPB : Time-base counter equal to counter-compare B (TBCNT = CMPB)
3h Disable EPWMxSYNCO signal