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SPRUH91D–March 2013–Revised September 2016
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External Memory Interface A (EMIFA)
18.2.12 Priority and Arbitration
Section 18.2.2 describes the external prioritization and arbitration among requests from different sources
within the SoC. The result of this external arbitration is that only one request is presented to the EMIFA at
a time. Once the EMIFA completes a request, the external arbiter then provides the EMIFA with the next
pending request.
Internally, the EMIFA undertakes memory device transactions according to a strict priority scheme. The
highest priority events are:
• A device reset.
• A write to any of the three least significant bytes of the SDRAM configuration register (SDCR).
Either of these events will cause the EMIFA to immediately commence its initialization sequence as
described in Section 18.2.4.4.
Once the EMIFA has completed its initialization sequence, it performs memory transactions according to
the following priority scheme (highest priority listed first):
1. If the EMIFA's backlog refresh counter is at the Refresh Must urgency level, the EMIFA performs
multiple SDRAM auto refresh cycles until the Refresh Release urgency level is reached.
2. If an SDRAM or asynchronous read has been requested, the EMIFA performs a read operation.
3. If the EMIFA's backlog refresh counter is at the Refresh Need urgency level, the EMIFA performs an
SDRAM auto refresh cycle.
4. If an SDRAM or asynchronous write has been requested, the EMIFA performs a write operation.
5. If the EMIFA's backlog refresh counter is at the Refresh May or Refresh Release urgency level, the
EMIFA performs an SDRAM auto refresh cycle.
6. If the value of the SR bit in SDCR has been set to 1, the EMIFA will enter the self-refresh state as
described in Section 18.2.4.7.
After taking one of the actions listed above, the EMIFA then returns to the top of the priority list to
determine its next action.
Because the EMIFA does not issue auto-refresh cycles when in the self-refresh state, the above priority
scheme does not apply when in this state. See Section 18.2.4.7 for details on the operation of the EMIFA
when in the self-refresh state.
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