www.ti.com
Setting Up a Transfer
569
SPRUH91D–March 2013–Revised September 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
Enhanced Direct Memory Access (EDMA3) Controller
16.6 Setting Up a Transfer
The following list provides a quick guide for the typical steps involved in setting up a transfer.
1. Initiating a DMA/QDMA channel:
(a) Determine the type of channel (QDMA or DMA) to be used.
(b) If using a QDMA channel, program the QDMA channel n mapping register (QCHMAPn) with the
parameter set number to which the channel maps and the trigger word.
(c) If the channel is being used in the context of a shadow region, ensure the DMA region access
enable register (DRAE) for the region is properly set up to allow read/write accesses to bits in the
event register and interrupt register in the shadow region memory-map. The subsequent steps in
this process should be done using the respective shadow region registers. (Shadow region
descriptions and usage are provided in Section 16.2.7.1.)
(d) Determine the type of triggering used.
(i) If external events are used for triggering (DMA channels), enable the respective event in EER
by writing into EESR.
(ii) If a QDMA channel is used, enable the channel in QEER by writing into QEESR.
(e) Queue setup.
(i) If a QDMA channel is used, set up QDMAQNUM to map the channel to the respective event
queue.
(ii) If a DMA channel is used, set up DMAQNUM to map the event to the respective event queue.
2. Parameter set setup: Program the PaRAM set number associated with the channel. Note that if it is a
QDMA channel, the PaRAM entry that is configured as trigger word is written last. Alternatively, enable
the QDMA channel just before the write to the trigger word.
See Section 16.3 for parameter set field setups for different types of transfers. See the sections on
chaining (Section 16.2.8) and interrupt completion (Section 16.2.9) on how to set up final/intermediate
completion chaining and/or interrupts.
3. Interrupt setup:
(a) If working in the context of a shadow region, ensure the relevant bits in DRAE are set.
(b) Enable the interrupt in IER by writing into IESR.
(c) Ensure that the EDMA3CC completion interrupt is enabled properly in the device interrupt
controller.
(d) Set up the interrupt controller properly to receive the expected EDMA3 interrupt.
4. Initiate transfer (this step is highly dependent on the event trigger source):
(a) If the source is an external event coming from a peripheral, the peripheral will be enabled to start
generating relevant EDMA3 events that can be latched to the ER transfer.
(b) For QDMA events, writes to the trigger word will initiate the transfer.
(c) Manually-triggered transfers will be initiated by writes to the event set register (ESR).
(d) Chained-trigger events initiate when a previous transfer returns a transfer completion code equal to
the chained channel number.
5. Wait for completion:
(a) If the interrupts are enabled as mentioned in step 3, then the EDMA3CC generates a completion
interrupt to the CPU whenever transfer completion results in setting the corresponding bits in the
interrupt pending register (IPR). The set bits must be cleared in IPR by writing to the corresponding
bit in ICR.
(b) If polling for completion (interrupts not enabled in the device controller), then the application code
can wait on the expected bits to be set in IPR. Again, the set bits in IPR must be manually cleared
by writing to ICR before the next set of transfers is performed for the same transfer completion
code values.
To Next Page
Loading...
