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SPRUH91D–March 2013–Revised September 2016
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Inter-Integrated Circuit (I2C) Module
22.3.18 I2C Pin Data In Register (ICPDIN)
The I2C pin data in register (ICPDIN) holds the I/O state of each of the I2C pins (I2Cx_SDA and
I2Cx_SCL); and should return the value from the pin's input buffer (with appropriate synchronization/DFT
considerations). However, this register allows the actual value of the pin to be read regardless of the state
of PFUNC or PDIR bits . ICPDIN is shown in Figure 22-32 and described in Table 22-25.
Figure 22-32. I2C Pin Data In Register (ICPDIN)
31 16
Reserved
R-0
15 2 1 0
Reserved PDIN1 PDIN0
R-0 R/W-0 R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 22-25. I2C Pin Data In Register (ICPDIN) Field Descriptions
Bit Field Value Description
31-2 Reserved 0 These reserved bit locations are always read as zeros. A value written to this field has no effect.
1 PDIN1 Indicates the logic level present on the I2Cx_SDA pin.
During reads:
0 Logic-low present at I2Cx_SDA pin, regardless of PFUNC bit setting.
1 Logic-high present at I2Cx_SDA pin, regardless of PFUNC bit setting.
During writes: Writes have no effect.
0 PDIN0 Indicates the logic level present on the I2Cx_SCL pin.
During reads:
0 Logic-low present at I2Cx_SCL pin, regardless of PFUNC bit setting.
1 Logic-high present at I2Cx_SCL pin, regardless of PFUNC bit setting.
During writes: Writes have no effect.
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