Texas Instruments TMS320C6745 DSP - QDMA Event Enable Clear Register (QEECR); QDMA Event Enable Set Register (QEESR); QDMA Event Enable Clear Register (QEECR) Field Descriptions; QDMA Event Enable Set Register (QEESR) Field Descriptions

www.ti.com Registers
543
SPRUH91D–March 2013–Revised September 2016
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
Enhanced Direct Memory Access (EDMA3) Controller
16.4.2.7.3 QDMA Event Enable Clear Register (QEECR)
The QDMA event enable register (QEER) cannot be modified by directly writing to the register, in order to
ease the software burden when multiple tasks are attempting to simultaneously modify these registers.
The QDMA event enable clear register (QEECR) is used to disable events. Writes of 1 to the bits in
QEECR clear the corresponding QDMA channel bits in QEER; writes of 0 have no effect.
The QEECR is shown in Figure 16-78 and described in Table 16-57.
Figure 16-78. QDMA Event Enable Clear Register (QEECR)
31 16
Reserved
R-0
15 8 7 6 5 4 3 2 1 0
Reserved E7 E6 E5 E4 E3 E2 E1 E0
R-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0
LEGEND: R = Read only; W = Write only; -n = value after reset
Table 16-57. QDMA Event Enable Clear Register (QEECR) Field Descriptions
Bit Field Value Description
31-8 Reserved 0 Reserved
7-0 En QDMA event enable clear for channels 0-7.
0 No effect.
1 QDMA event is disabled. Corresponding bit in the QDMA event enable register (QEER) is cleared
(En = 0).
16.4.2.7.4 QDMA Event Enable Set Register (QEESR)
The QDMA event enable register (QEER) cannot be modified by directly writing to the register, in order to
ease the software burden when multiple tasks are attempting to simultaneously modify these registers.
The QDMA event enable set register (QEESR) is used to enable events. Writes of 1 to the bits in QEESR
set the corresponding QDMA channel bits in QEER; writes of 0 have no effect.
The QEESR is shown in Figure 16-79 and described in Table 16-58.
Figure 16-79. QDMA Event Enable Set Register (QEESR)
31 16
Reserved
R-0
15 8 7 6 5 4 3 2 1 0
Reserved E7 E6 E5 E4 E3 E2 E1 E0
R-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0
LEGEND: R = Read only; W = Write only; -n = value after reset
Table 16-58. QDMA Event Enable Set Register (QEESR) Field Descriptions
Bit Field Value Description
31-8 Reserved 0 Reserved
7-0 En QDMA event enable set for channels 0-7.
0 No effect.
1 QDMA event is enabled. Corresponding bit in the QDMA event enable register (QEER) is set (En = 1).