Texas Instruments TMS320C6745 DSP - 14.4 Registers; 14.4.1 Time-Base Submodule Registers; Time-Base Control Register (TBCTL); Submodule Registers

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SPRUH91D–March 2013–Revised September 2016
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Enhanced High-Resolution Pulse-Width Modulator (eHRPWM)
14.4 Registers
This section includes the registers for the submodules.
Table 14-50. Submodule Registers
Submodule Section
Time-Base Submodule Registers Section 14.4.1
Counter-Compare Submodule Registers Section 14.4.2
Action-Qualifier Submodule Registers Section 14.4.3
Dead-Band Generator Submodule Registers Section 14.4.4
PWM-Chopper Submodule Registers Section 14.4.5
Trip-Zone Submodule Registers Section 14.4.6
Event-Trigger Submodule Registers Section 14.4.7
High-Resolution PWM Registers Section 14.4.8
14.4.1 Time-Base Submodule Registers
Table 14-51 lists the memory-mapped registers for the time-base submodule. See your device-specific
data manual for the memory address of these registers. All other register offset addresses not listed in
Table 14-51 should be considered as reserved locations and the register contents should not be modified.
(1)
This register is only available on ePWM instances that include the high-resolution PWM (HRPWM) extension; otherwise, this
location is reserved. See your device-specific data manual to determine which instances include the HRPWM.
Table 14-51. Time-Base Submodule Registers
Offset Acronym Register Description Section
0h TBCTL Time-Base Control Register Section 14.4.1.1
2h TBSTS Time-Base Status Register Section 14.4.1.2
4h TBPHSHR Time-Base Phase High-Resolution Register
(1)
Section 14.4.8.1
6h TBPHS Time-Base Phase Register Section 14.4.1.3
8h TBCNT Time-Base Counter Register Section 14.4.1.4
Ah TBPRD Time-Base Period Register Section 14.4.1.5
14.4.1.1 Time-Base Control Register (TBCTL)
The time-base control register (TBCTL) is shown in Figure 14-65 and described in Table 14-52.
Figure 14-65. Time-Base Control Register (TBCTL)
15 14 13 12 10 9 8
FREE, SOFT PHSDIR CLKDIV HSPCLKDIV
R/W-0 R/W-0 R/W-0 R/W-0
7 6 5 4 3 2 1 0
HSPCLKDIV SWFSYNC SYNCOSEL PRDLD PHSEN CTRMODE
R/W-1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-3h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset