Texas Instruments TMS320C6745 DSP - EDMA3 Channel Controller (EDMA3 CC) Block Diagram

Event
register
(ER)
Event
enable
register
(EER)
Event
set
register
(ESR)
Chained
event
register
(CER)
QDMA
event
register
(QER)
32
32
32
32:1priorityencoder
8:1priorityencoder
8
Queue0
Eventqueues
Channelmapping
Queuebypass
Parameter
set0
Parameter
set1
set127
Parameter
Parameter
set126
Transferrequestsubmission
PaRAM
E31 E0E1
To
EDMA3TC(s)
From
EDMA3TC(s)
Completion
interface
Completion
detection
Event
trigger
Manual
trigger
Chain
trigger
QDMA trigger
Completion
interruptdetection
Error
EDMA3CC_ERRINT EDMA3CC_INT[1:0]
EDMA3channel
controller
Fromperipherals/externalevents
15 0
Queue1
15 0
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SPRUH91D–March 2013–Revised September 2016
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Enhanced Direct Memory Access (EDMA3) Controller
Figure 16-2. EDMA3 Channel Controller (EDMA3CC) Block Diagram
Each event in the event queue is processed in the order it was queued. On reaching the head of the
queue, the PaRAM associated with that channel is read to determine the transfer details. The TR
submission logic evaluates the validity of the TR and is responsible for submitting a valid transfer request
(TR) to the appropriate EDMA3TC (based on the event queue to EDMA3TC association, Q0 goes to TC0,
and Q1 goes to TC1, etc.). For more details, see Section 16.2.3.
The EDMA3TC receives the request and is responsible for data movement as specified in the transfer
request packet (TRP) and other necessary tasks like buffering, ensuring transfers are carried out in an
optimal fashion wherever possible. For more details on EDMA3TC, see Section 16.2.1.2.
You may have chosen to receive an interrupt or chain to another channel on completion of the current
transfer in which case the EDMA3TC signals completion to the EDMA3CC completion detection logic
when the transfer is done. You can alternately choose to trigger completion when a TR leaves the
EDMA3CC boundary rather than wait for all the data transfers to complete. Based on the setting of the
EDMA3CC interrupt registers, the completion interrupt generation logic is responsible for generating
EDMA3CC completion interrupts to the CPU. For more details, see Section 16.2.5.
Additionally, the EDMA3CC also has an error detection logic, which causes error interrupt generation on
various error conditions (like missed events, exceeding event queue thresholds, etc.). For more details on
error interrupts, see Section 16.2.9.4.