Texas Instruments TMS320C6745 DSP - Power Domain 0 Configuration Register (PDCFG0); Power Domain 0 Configuration Register (PDCFG0) Field Descriptions

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Power and Sleep Controller (PSC)
8.6.15 Power Domain 0 Configuration Register (PDCFG0)
The power domain 0 configuration register (PDCFG0) is shown in Figure 8-15 and described in
Table 8-20.
Figure 8-15. Power Domain 0 Configuration Register (PDCFG0)
31 16
Reserved
R-0
15 4 3 2 1 0
Reserved PD_LOCK ICEPICK RAM_PSM ALWAYSON
R-0 R-1 R-1 R-0 R-1
LEGEND: R = Read only; -n = value after reset
Table 8-20. Power Domain 0 Configuration Register (PDCFG0) Field Descriptions
Bit Field Value Description
31-4 Reserved 0 Reserved
3 PD_LOCK PDCTL.NEXT lock. For Always ON power domain this bit is a don't care.
0 PDCTL.NEXT bit is locked and cannot be changed in software.
1 PDCTL.NEXT bit is not locked.
2 ICEPICK IcePick support.
0 Not present
1 Present
1 RAM_PSM RAM power domain.
0 Not a RAM power domain.
1 RAM power domain.
0 ALWAYSON Always ON power domain.
0 Not an Always ON power domain.
1 Always ON power domain.