Texas Instruments TMS320C6745 DSP - MMC Status Register 0 (MMCST0); MMC Status Register 0 (MMCST0) Field Descriptions

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SPRUH91D–March 2013–Revised September 2016
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Multimedia Card (MMC)/Secure Digital (SD) Card Controller
25.4.3 MMC Status Register 0 (MMCST0)
The MMC status register 0 (MMCST0) records specific events or errors. The transition from 0 to 1 on each
bit in MMCST0 can cause an interrupt signal to be sent to the CPU. If an interrupt is desired, set the
corresponding interrupt enable bit in the MMC interrupt mask register (MMCIM).
In most cases, when a status bit is read, it is cleared. The two exceptions are the DRRDY bit and the
DXRDY bit; these bits are cleared only in response to the functional events described for them in
Table 25-8, or in response to a hardware reset.
The MMC status register 0 (MMCST0) is shown in Figure 25-19 and described in Table 25-8.
NOTE: 1) As the command portion and the data portion of the MMC/SD controller are independent,
any command such as CMD0 (GO_IDLE_STATE) or CMD12 (STOP_TRANSMISSION) can
be sent to the card, even during block transfer. In this situation, the data portion detects this
and waits, releasing the busy state only when the command sent was R1b (to be specific,
command with BSYEXP bit), otherwise it continues transferring data.
2) Bit 12 (TRNDNE) indicates that the last byte of a transfer has been completed. Bit 0
(DATDNE) occurs at end of a transfer, but not until the CRC check and programming has
completed.
Figure 25-19. MMC Status Register 0 (MMCST0)
31 16
Reserved
R-0
15 14 13 12 11 10 9 8
Reserved CCS TRNDNE DATED DRRDY DXRDY Reserved
R-0 R-0 R-0 RC-0 R-0 R-1 R-0
7 6 5 4 3 2 1 0
CRCRS CRCRD CRCWR TOUTRS TOUTRD RSPDNE BSYDNE DATDNE
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
LEGEND: R = Read only; RC = Cleared to 0 when read; -n = value after reset
Table 25-8. MMC Status Register 0 (MMCST0) Field Descriptions
Bit Field Value Description
31-14 Reserved 0 Reserved
13 CCS Command completion signal
0 Command completion signal is not completed.
1 Command completion signal is completed.
12 TRNDNE Transfer done.
0 No data transfer is done.
1 Data transfer of specified length is done.
11 DATED MMCSD_DAT3 edge detected. DATED is cleared when read by CPU.
0 An MMCSD_DAT3 edge has not been detected.
1 An MMCSD_DAT3 edge has been detected.
10 DRRDY Data receive ready. DRRDY is cleared to 0 when the DAT logic is reset (DATRST = 1 in MMCCTL),
when a command is sent with data receive/transmit clear (DCLR = 1 in MMCCMD), or when data is
read from the MMC data receive register (MMCDRR).
0 MMCDRR is not ready.
1 MMCDRR is ready. New data has arrived and can be read by the CPU or by the DMA controller.