Texas Instruments TMS320C6745 DSP - SDRAM Self Refresh Exit Timing Register (SDSRETR); SDRAM Self Refresh Exit Timing Register (SDSRETR) Field Descriptions

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767
SPRUH91D–March 2013–Revised September 2016
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External Memory Interface A (EMIFA)
18.4.7 SDRAM Self Refresh Exit Timing Register (SDSRETR)
The SDRAM self refresh exit timing register (SDSRETR) is used to program the amount of time between
when the SDRAM exits Self-Refresh mode and when the EMIFA issues another command. The
SDSRETR is shown in Figure 18-37 and described in Table 18-55.
Figure 18-37. SDRAM Self Refresh Exit Timing Register (SDSRETR)
31 16
Reserved
R-0
15 5 4 0
Reserved T_XS
R-0 R/W-9h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 18-55. SDRAM Self Refresh Exit Timing Register (SDSRETR) Field Descriptions
Bit Field Value Description
31-5 Reserved 0 Reserved. The reserved bit location is always read as 0.
4-0 T_XS 0-1Fh This field specifies the minimum number of ECLKOUT cycles from Self-Refresh exit to any command,
minus one.
T_XS = Txsr / t
EMA_CLK
- 1