Texas Instruments TMS320C6745 DSP - SDRAM Configuration Register (SDCFG); SDRAM Configuration Register (SDCFG) Field Descriptions

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SPRUH91D–March 2013–Revised September 2016
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External Memory Interface B (EMIFB)
19.4.1 SDRAM Configuration Register (SDCFG)
The SDRAM configuration register (SDCFG) is used to configure various parameters of the SDRAM
controller such as the number of internal banks, the internal page size, and the CAS latency to match
those of the attached SDRAM device. The SDCFG is shown in Figure 19-14 and described in
Table 19-25.
BOOT_UNLOCK bit usage - The following sequence must be followed to change the value of the SDREN
and MSDRAM_ENABLE bits.
1. Set the BOOT_UNLOCK bit to 1.
2. Write a 0 to the BOOT_UNLOCK bit along with the desired values for the SDREN/MSDRAM_ENABLE
bits. The value of the bits is then updated.
TIMUNLOCK bit usage - The following sequence must be followed to change the value of any field
affected by the TIMUNLOCK bit.
1. Write a 1 to the TIMUNLOCK bit along with the desired value for the CL field. The value of the CL field
is then updated.
2. Update any of the fields required in the SDRAM timing registers (SDTIM1 and SDTIM2).
3. Clear the TIMUNLOCK bit to 0 to prevent any further changes.
NOTE: Writing to the lower two bytes of this register will cause the EMIF to start the SDRAM
initialization sequence.
Figure 19-14. SDRAM Configuration Register (SDCFG)
31 27 26 25 24
Reserved IBANK_POS MSDRAM_ENABLE Reserved
R-0 R/W-0 R/W-0 R-0
23 22 17 16
BOOT_UNLOCK Reserved SDREN
R/W-0 R-0 R/W-1
15 14 13 12 11 9 8
TIMUNLOCK NM Reserved CL Reserved
R/W-0 R/W-0 R-0 R/W-3h R-0
7 6 4 3 2 0
Reserved IBANK EBANK PAGESIZE
R-0 R/W-2h R/W-0 R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 19-25. SDRAM Configuration Register (SDCFG) Field Descriptions
Bit Field Value Description
31-27 Reserved 0 All writes to these bit(s) must always have a value of 0.
26 IBANK_POS Internal bank position. This bit is writeable only when the BOOT_UNLOCK bit is unlocked.
0 Set to 0 to assign internal bank address bits from logical address as shown in Table 19-14
and Table 19-15. Set this bit to 0 when interfacing with SDR SDRAM.
1 Set to 1 to assign internal bank address bits from logical address as shown in Table 19-16.
Set this bit to 1 when interfacing with mobile SDRAM.
25 MSDRAM_ENABLE Mobile SDRAM Enable. This bit is writeable only when the BOOT_UNLOCK bit is unlocked.
For mobile SDR SDRAM, this bit is only valid when SDREN is set to 1.
0 mSDR (mobile SDR) is disabled.
1 When this bit is 1 and SDREN = 1, then mSDR is enabled.
24 Reserved 0 All writes to these bit(s) must always have a value of 0.