16 KBytes data transfer
Event 25 (CPU writes 1 to ESR.E25)
ACNT = 16384
BCNT = 1
CCNT = 1
1D transfer of 16 KByte elements
OPT.ITCINTEN = 0
OPT.TCC = Don’t care
EDMA3 channel 25 setup
Channel 16, array 0
Intermediate
transfer complete
(A)
Channel 31, array 0
Event 16
Hardwired event
(tied to GPINT0, event 16)
Chained event
(event 31)
Channel 16, array 1
Event 16
Channel 31, array 1
Intermediate
transfer complete
(A)
Channel 31, array 3
Channel 16, array 3
Channel 16, array 2
Event 16
Event 16
Channel 31, array 2
Transfer complete
(B)
Intermediate
transfer complete
(A)
(last array)
Transfer complete sets
IPR.I31 = 1
If IPR.I31 = 1,
EDMACC_INT sent
Notes:
(A) Intermediate transfer complete chaining synchronizes event 31
ITCCHEN = 1, TCC = 001 1111b and sets CER.E31 = 1
(B) Transfer complete chaining synchronizes event 31
TCCHEN = 1, TCC = 001 1111b and sets CER.E31 = 1
to CPU
Enable transfer
complete chaining:
OPT.TCCHEN = 1
OPT.TCC = 001 1111b
Enable intermediate transfer
complete chaining:
OPT.ITCCHEN = 1
OPT.TCC = 001 1111b
Disable intermediate transfer
OPT.TCINTEN = 1
OPT.ITCCHEN = 0
complete chaining:
OPT.TCC = 001 1111b
completion interrupt:
Enable transfer
Setup
Channel 16 parameters
for chaining for chaining
Channel 16 parameters
Enable channel 16
EER.E16 = 1
Event enable register (EER)
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Transfer Examples
499
SPRUH91D–March 2013–Revised September 2016
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Enhanced Direct Memory Access (EDMA3) Controller
Figure 16-32. Intermediate Transfer Completion Chaining Example
Figure 16-33. Single Large Block Transfer Example
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