Transfer Examples
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SPRUH91D–March 2013–Revised September 2016
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Enhanced Direct Memory Access (EDMA3) Controller
16.3.4.5 Transfer Chaining Examples
The following examples explain the intermediate transfer complete chaining function.
16.3.4.5.1 Servicing Input/Output FIFOs with a Single Event
Many systems require the use of a pair of external FIFOs that must be serviced at the same rate. One
FIFO buffers data input, and the other buffers data output. The EDMA3 channels that service these FIFOs
can be set up for AB-synchronized transfers. While each FIFO is serviced with a different set of
parameters, both can be signaled from a single event. For example, an external interrupt pin can be tied
to the status flags of one of the FIFOs. When this event arrives, the EDMA3 needs to perform servicing for
both the input and output streams. Without the intermediate transfer complete chaining feature this would
require two events, and thus two external interrupt pins. The intermediate transfer complete chaining
feature allows the use of a single external event (for example, a GPIO event). Figure 16-32 shows the
EDMA3 setup and illustration for this example.
A GPIO event (in this case, GPINT0) triggers an array transfer. Upon completion of each intermediate
array transfer of channel 16, intermediate transfer complete chaining sets the E31 bit (specified by TCC of
31) in the chained event register (CER) and provides a synchronization event to channel 31. Upon
completion of the last array transfer of channel 16, transfer complete chaining—not intermediate transfer
complete chaining—sets the E31 bit in CER (specified by TCCMODE:TCC) and provides a
synchronization event to channel 31. The completion of channel 31 sets the I31 bit (specified by
TCCMODE:TCC) in the interrupt pending register (IPR), which can generate an interrupt to the CPU, if the
I31 bit in the interrupt enable register (IER) is set to 1.
16.3.4.5.2 Breaking Up Large Transfers with Intermediate Chaining
Another feature of intermediate transfer chaining (ITCCHEN) is for breaking up large transfers. A large
transfer may lock out other transfers of the same priority level for the duration of the transfer. For example,
a large transfer on queue 0 from the internal memory to the external memory using the EMIF may starve
other EDMA3 transfers on the same queue. In addition, this large high-priority transfer may prevent the
EMIF for a long duration to service other lower priority transfers. When a large transfer is considered to be
high priority, it should be split into multiple smaller transfers. Figure 16-33 shows the EDMA3 setup and
illustration of an example single large block transfer.
The intermediate transfer chaining enable (ITCCHEN) provides a method to break up a large transfer into
smaller transfers. For example, to move a single large block of memory (16K bytes), the EDMA3 performs
an A-synchronized transfer. The element count is set to a reasonable value, where reasonable derives
from the amount of time it would take to move this smaller amount of data. Assume 1K byte is a
reasonable small transfer in this example. The EDMA3 is set up to transfer 16 arrays of 1K byte elements,
for a total of 16K byte elements. The TCC field in the channel options parameter (OPT) is set to the same
value as the channel number and ITCCHEN are set. In this example, DMA channel 25 is used and TCC is
also set to 25. The TCINTEN may also be set to trigger interrupt 25 when the last 1K byte array is
transferred. The CPU starts the EDMA3 transfer by writing to the appropriate bit of the event set register
(ESR.E25). The EDMA3 transfers the first 1K byte array. Upon completion of the first array, intermediate
transfer complete code chaining generates a synchronization event to channel 25, a value specified by the
TCC field. This intermediate transfer completion chaining event causes DMA channel 25 to transfer the
next 1K byte array. This process continues until the transfer parameters are exhausted, at which point the
EDMA3 has completed the 16K byte transfer. This method breaks up a large transfer into smaller packets,
thus providing natural time slices in the transfer such that other events may be processed. Figure 16-34
shows the EDMA3 setup and illustration of the broken up smaller packet transfers.
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