Registers
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SPRUH91D–March 2013–Revised September 2016
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Enhanced Direct Memory Access (EDMA3) Controller
16.4.2.5.4 Chained Event Register (CER)
When the OPTIONS parameter for a PaRAM entry is programmed to returned a chained completion code
(ITCCHEN = 1 and/or TCCHEN = 1), then the value dictated by the TCC[5:0] (also programmed in OPT)
forces the corresponding event bit to be set in the chained event register (CER). The set chained event is
evaluated by the EDMA3CC logic for an associated transfer request submission to the transfer controllers.
This results in a chained-triggered transfer.
The chained event registers do not have any enables. The generation of a chained event is essentially
enabled by the PaRAM entry that has been configured for intermediate and/or final chaining on transfer
completion. The En bit is set (regardless of the state of EER.En) when a chained completion code is
returned from one of the transfer controllers or is generated by the EDMA3CC via the early completion
path. The bits in the chained event register are cleared when the corresponding events are prioritized and
serviced.
If the En bit is already set and another chaining completion code is return for the same event, then the
corresponding event is latched in the event missed register (EMR.En = 1). The setting of an event is a
higher priority relative to clear operations (via hardware). If set and clear conditions occur concurrently, the
set condition wins. If the event was previously set, then EMR would be set since an event is lost. If the
event was previously clear, then the event remains set and is prioritized for submission to the event
queues.
The CER is shown in Figure 16-64 and described in Table 16-43.
Figure 16-64. Chained Event Register (CER)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
E31 E30 E29 E28 E27 E26 E25 E24 E23 E22 E21 E20 E19 E18 E17 E16
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
E15 E14 E13 E12 E11 E10 E9 E8 E7 E6 E5 E4 E3 E2 E1 E0
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
LEGEND: R = Read only; -n = value after reset
Table 16-43. Chained Event Register (CER) Field Descriptions
Bit Field Value Description
31-0 En Chained event for event 0-31.
0 No effect.
1 Corresponding DMA event is prioritized versus other pending DMA/QDMA events for submission to the
EDMA3TC.
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