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SPRUH91D–March 2013–Revised September 2016
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Universal Asynchronous Receiver/Transmitter (UART)
29.3.2 Transmitter Holding Register (THR)
The transmitter holding register (THR) is shown in Figure 29-10 and described in Table 29-8.
The UART transmitter section consists of a transmitter hold register (THR) and a transmitter shift register
(TSR). When the UART is in the FIFO mode, THR is a 16-byte FIFO. Transmitter section control is a
function of the line control register (LCR).
THR receives data from the internal data bus and when TSR is idle, the UART moves the data from THR
to TSR. The UART serializes the data in TSR and transmits the data on the TX pin. In the non-FIFO
mode, if THR is empty and the THR empty (THRE) interrupt is enabled (ETBEI = 1 in IER), an interrupt is
generated. This interrupt is cleared when a character is loaded into THR or the interrupt identification
register (IIR) is read. In the FIFO mode, the interrupt is generated when the transmitter FIFO is empty,
and it is cleared when at least one byte is loaded into the FIFO or IIR is read.
Access considerations:
RBR, THR, and DLL share one address. To load THR, write 0 to the DLAB bit of LCR, and write to the
shared address. When DLAB = 0, reading from the shared address gives the content of RBR. When
DLAB = 1, all accesses at the address read or modify DLL.
DLL also has a dedicated address. If you use the dedicated address, you can keep DLAB = 0, so that
RBR and THR are always selected at the shared address.
Figure 29-10. Transmitter Holding Register (THR)
31 16
Reserved
R-0
15 8 7 0
Reserved DATA
R-0 W-0
LEGEND: R = Read only; W = Write only; -n = value after reset
Table 29-8. Transmitter Holding Register (THR) Field Descriptions
Bit Field Value Description
31-8 Reserved 0 Reserved
7-0 DATA 0-FFh Data to transmit
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