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Registers
511
SPRUH91D–March 2013–Revised September 2016
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Enhanced Direct Memory Access (EDMA3) Controller
Table 16-22. EDMA3CC Configuration Register (CCCFG) Field Descriptions
Bit Field Value Description
31-26 Reserved 0-3Fh Reserved
25 MP_EXIST Memory protection existence.
0 No memory protection.
1 Reserved
24 CHMAP_EXIST Channel mapping existence.
0 No channel mapping. This implies that there is fixed association for a channel number to a
parameter entry number or, in other words, PaRAM entry n corresponds to channel n.
1 Reserved
23-22 Reserved 0 Reserved
21-20 NUM_REGN 0-3h Number of shadow regions.
0-1h Reserved
2h 4 regions
3h Reserved
19 Reserved 0 Reserved
18-16 NUM_EVQUE 0-7h Number of queues/number of transfer controllers.
0 Reserved
1h 2 event queues
2h 2 transfer controllers
3h-7h Reserved
15 Reserved 0 Reserved
14-12 NUM_PAENTRY 0-7h Number of PaRAM sets.
0-2h Reserved
3h 128 PaRAM sets
4h-7h Reserved
11 Reserved 0 Reserved
10-8 NUM_INTCH 0-7h Number of interrupt channels.
0-2h Reserved
3h 32 interrupt channels
4h-7h Reserved
7 Reserved 0 Reserved
6-4 NUM_QDMACH 0-7h Number of QDMA channels.
0-3h Reserved
4h 8 QDMA channels
5h-7h Reserved
3 Reserved 0 Reserved
2-0 NUM_DMACH 0-7h Number of DMA channels.
0-3h Reserved
4h 32 DMA channels
5h-7h Reserved