Texas Instruments TMS320C6745 DSP - Interrupt Enable Status;Clear Register (IENSTAT); Interrupt Enable Status;Clear Register (IENSTAT) Field Descriptions

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SPRUH91D–March 2013–Revised September 2016
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Memory Protection Unit (MPU)
5.3.4 Interrupt Enable Status/Clear Register (IENSTAT)
Reading the interrupt enable status/clear register (IENSTAT) returns the status of only those interrupts
that are enabled in the interrupt enable set register (IENSET). Software can write to IENSTAT to clear an
interrupt; the interrupt is cleared from both IENSTAT and the interrupt raw status/set register
(IRAWSTAT). Writes of 0 have no effect. The IENSTAT is shown in Figure 5-6 and described in Table 5-
11.
Figure 5-6. Interrupt Enable Status/Clear Register (IENSTAT)
31 16
Reserved
R-0
15 2 1 0
Reserved ADDRERR PROTERR
R-0 R/W-0 R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 5-11. Interrupt Enable Status/Clear Register (IENSTAT) Field Descriptions
Bit Field Value Description
31-2 Reserved 0 Reserved
1 ADDRERR Address violation error. If the interrupt is enabled, reading this bit reflects the status of the interrupt.
If the interrupt is disabled, reading this bit returns 0. Writing 1 sets the status; writing 0 has no
effect.
0 Interrupt is not set.
1 Interrupt is set.
0 PROTERR Protection violation error. If the interrupt is enabled, reading this bit reflects the status of the
interrupt. If the interrupt is disabled, reading this bit returns 0. Writing 1 sets the status; writing 0
has no effect.
0 Interrupt is not set.
1 Interrupt is set.