Texas Instruments TMS320C6745 DSP - MMC Status Register 1 (MMCST1); MMC Status Register 1 (MMCST1) Field Descriptions

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SPRUH91D–March 2013–Revised September 2016
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Multimedia Card (MMC)/Secure Digital (SD) Card Controller
25.4.4 MMC Status Register 1 (MMCST1)
The MMC status register 1 (MMCST1) records specific events or errors. There are no interrupts
associated with these events or errors.
The MMC status register 1 (MMCST1) is shown in Figure 25-20 and described in Table 25-9.
Figure 25-20. MMC Status Register 1 (MMCST1)
31 16
Reserved
R-0
15 8
Reserved
R-0
7 6 5 4 3 2 1 0
Reserved FIFOFUL FIFOEMP DAT3ST DRFUL DXEMP CLKSTP BUSY
R-0 R-0 R-0 R-0 R-0 R-0 R-1 R-0
LEGEND: R = Read only; -n = value after reset
Table 25-9. MMC Status Register 1 (MMCST1) Field Descriptions
Bit Field Value Description
31-7 Reserved 0 Reserved
6 FIFOFUL FIFO is full.
0 FIFO is not full.
1 FIFO is full.
5 FIFOEMP FIFO is empty.
0 FIFO is not empty.
1 FIFO is empty.
4 DAT3ST MMCSD_DAT3 status.
0 The signal level on the MMCSD_DAT3 pin is a logic-low level.
1 The signal level on the MMCSD_DAT3 pin is a logic-high level.
3 DRFUL Data receive register (MMCDRR) is full.
0 A data receive register full condition is not detected. The data receive shift register is not full.
1 A data receive register full condition is detected. The data receive shift register is full. No new bits can
be shifted in from the memory card.
2 DXEMP Data transmit register (MMCDXR) is empty.
0 A data transmit register empty condition is not detected. The data transmit shift register is not empty.
1 A data transmit register empty condition is detected. The data transmit shift register is empty. No bits
are available to be shifted out to the memory card.
1 CLKSTP Clock stop status.
0 MMCSD_CLK is active. The memory clock signal is being driven on the pin.
1 MMCSD_CLK is held low because of a manual stop (CLKEN = 0 in MMCCLK), receive shift register is
full, or transmit shift register is empty.
0 BUSY Busy.
0 No busy signal is detected.
1 A busy signal is detected (the memory card is busy).