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SPRUH91D–March 2013–Revised September 2016
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Enhanced Direct Memory Access (EDMA3) Controller
16.2.12 Event Dataflow
This section summarizes the data flow of a single event, from the time the event is latched to the channel
controller to the time the transfer completion code is returned. The following steps list the sequence of
EDMA3CC activity:
1. Event is asserted from an external source (peripheral or external interrupt). This also is similar for a
manually-triggered, chained-triggered, or QDMA-triggered event. The event is latched into the ER.En
(or CER.En, ESR.En, QER.En) bit.
2. Once an event is prioritized and queued into the appropriate event queue, the SER.En (or QSER.En)
bit is set to inform the event prioritization/processing logic to disregard this event since it is already in
the queue. Alternatively, if the transfer controller and the event queue are empty, then the event
bypasses the queue.
3. The EDMA3CC processing and the submission logic evaluates the appropriate PaRAM set and
determines whether it is a non-null and non-dummy transfer request (TR).
4. The EDMA3CC clears the ER.En (or CER.En, ESR.En, QER.En) bit and the SER.En bit as soon as it
determines the TR is non-null. In the case of a null set, the SER.En bit remains set. It submits the non-
null/non-dummy TR to the associated transfer controller. If the TR was programmed for early
completion, the EDMA3CC immediately sets the interrupt pending register (IPR.I[TCC]).
5. If the TR was programmed for normal completion, the EDMA3CC sets the interrupt pending register
(IPR.I[TCC]) when the EDMA3TC informs the EDMA3CC about completion of the transfer (returns
transfer completion codes).
6. The EDMA3CC programs the associated EDMA3TCn Program Register Set with the TR.
7. The TR is then passed to the Source Active set and the Dst FIFO Register Set, if both the register sets
are available.
8. The Read Controller processes the TR by issuing read commands to the source slave endpoint. The
Read Data lands in the Data FIFO of the EDMA3TCn.
9. As soon as sufficient data is available, the Write Controller begins processing the TR by issuing write
commands to the destination slave endpoint.
10. This continues until the TR completes and on receiving the acknowledgement signal from the
destination slave end point, the EDMA3TCn then signals completion status to the EDMA3CC.
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