EMA_CS[0]
EMA_CAS
EMA_RAS
EMA_WE
EMA_CLK
EMA_SDCKE
EMA_BA[0]
EMA_A[10:0]
EMA_WE_DQM[0]
EMA_WE_DQM[1]
EMA_D[15:0]
EMIFA
CE
CAS
RAS
WE
CLK
CKE
BA[0]
A[10:0]
LDQM
UDQM
DQ[15:0]
SDRAM
512 x 16
x 2 bank
EMA_CS[0]
EMA_CAS
EMA_RAS
EMA_WE
EMA_CLK
EMA_SDCKE
EMA_BA[1:0]
EMA_A[11:0]
EMA_WE_DQM[0]
EMA_WE_DQM[1]
EMA_D[15:0]
EMIFA
CE
CAS
RAS
WE
CLK
CKE
BA[1:0]
A[11:0]
LDQM
UDQM
DQ[15:0]
SDRAM
2M x 16
x 4 bank
Architecture
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SPRUH91D–March 2013–Revised September 2016
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External Memory Interface A (EMIFA)
Figure 18-3. EMIFA to 2M × 16 × 4 bank SDRAM Interface
Figure 18-4. EMIFA to 512K × 16 × 2 bank SDRAM Interface
Table 18-6. 16-bit EMIFA Address Pin Connections
SDRAM Size Width Banks Device Address Pins
16M bits ×16 2 SDRAM A[10:0]
EMIFA EMA_A[10:0]
64M bits ×16 4 SDRAM A[11:0]
EMIFA EMA_A[11:0]
128M bits ×16 4 SDRAM A[11:0]
EMIFA EMA_A[11:0]
256M bits x16 4 SDRAM A[12:0]
EMIFA EMA_A[12:0]
512M bits x16 4 SDRAM A[12:0]
EMIFA EMA_A[12:0]