Texas Instruments TMS320C6745 DSP - DMA Region Access Enable Register for Region M (Draem); DMA Region Access Enable Register for Region M (Draem) Field Descriptions

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SPRUH91D–March 2013–Revised September 2016
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Enhanced Direct Memory Access (EDMA3) Controller
16.4.2.3 Region Access Enable Registers
The region access enable register group consists of the DMA access enable registers (DRAEm) and the
QDMA access enable registers (QRAEm). Where m is the number of shadow regions in the EDMA3CC
memory-map for a device. You can configure these registers to assign ownership of DMA/QDMA channels
to a particular shadow region.
16.4.2.3.1 DMA Region Access Enable for Region m (DRAEm)
The DMA region access enable registers for shadow region m (DRAEm) is programmed to allow or
disallow read/write accesses on a bit-by-bit bases for all DMA registers in the shadow region m view of the
DMA channel registers. See the EDMA3CC register memory-map for a list of all the DMA channel and
interrupt registers mapped in the shadow region view. Additionally, the DRAEm configuration determines
completion of which DMA channels will result in assertion of the shadow region m DMA completion
interrupt (see Section 16.2.9).
The DRAEm is shown in Figure 16-55 and described in Table 16-34.
Figure 16-55. DMA Region Access Enable Register for Region m (DRAEm)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
E31 E30 E29 E28 E27 E26 E25 E24 E23 E22 E21 E20 E19 E18 E17 E16
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
E15 E14 E13 E12 E11 E10 E9 E8 E7 E6 E5 E4 E3 E2 E1 E0
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
Table 16-34. DMA Region Access Enable Register for Region m (DRAEm) Field Descriptions
Bit Field Value Description
31-0 En DMA region access enable for bit n/channel n in region m.
0 Accesses via region m address space to bit n in any DMA channel register are not allowed. Reads
return 0 on bit n and writes do not modify the state of bit n. Enabled interrupt bits for bit n do not
contribute to the generation of a transfer completion interrupt for shadow region m.
1 Accesses via region m address space to bit n in any DMA channel register are allowed. Reads return
the value from bit n and writes modify the state of bit n. Enabled interrupt bits for bit n contribute to the
generation of a transfer completion interrupt for shadow region m.